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ATXMEGA256A1 Datasheet(PDF) 11 Page - ATMEL Corporation |
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ATXMEGA256A1 Datasheet(HTML) 11 Page - ATMEL Corporation |
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11 / 82 page  11 8067D–AVR–08/08 XMEGA A1 7.4.1 I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the CPU and the I/O Memory. The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc- tions on these registers. The I/O memory address for all peripherals and modules in XMEGA A1 is shown in the “Periph- eral Module Address Map” on page 54. 7.4.2 SRAM Data Memory The XMEGA A1 devices has internal SRAM memory for data storage. 7.4.3 EEPROM Data Memory The XMEGA A1 devices has internal EEPROM memory for non-volatile data storage. It is addressable either in a separate data space or it can be memory mapped into the normal data memory space. The EEPROM memory supports both byte and page access. Byte Address ATxmega384A1 Byte Address ATxmega256A1 0 I/O Registers (4KB) 0 I/O Registers (4KB) FFF FFF 1000 EEPROM (4K) 1000 EEPROM (4K) 1FFF 1FFF 2000 Internal SRAM (32K) 2000 Internal SRAM (16K) 9FFF 5FFF 10000 External Memory (0 to 16 MB) 6000 External Memory (0 to 16 MB) FFFFFF FFFFFF |
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