CY7C68013
Document #: 38-08012 Rev. *B
Page 6 of 50
— Three counter/timers
— Expanded interrupt system
— Two data pointers
• 3.3V operation
• Smart Serial Interface Engine
• Vectored USB interrupts
• Separate data buffers for the SETUP and DATA portions of a CONTROL transfer
• Integrated I2C-compatible controller, runs at 100 or 400 kHz
• 48-MHz, 24-MHz, or 12-MHz 8051 operation
• Four integrated FIFOs
— Brings glue and FIFOs inside for lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— FIFOs can use externally supplied clock or asynchronous strobes
— Easy interface to ASIC and DSP ICs
• Special autovectors for FIFO and GPIF interrupts
• Up to 40 general purpose I/Os
• Four package options—128-pin TQFP, 100-pin TQFP, 56-pin QFN and 56-pin SSOP.
2.0
Applications
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Home PNA
• Wireless LAN
• MP3 players
• Networking.
The “Reference Designs” section of the cypress website provides additional tools for typical USB 2.0 applications. Each reference
design
comes
complete
with
firmware
source
and
object
code,
schematics,
and
documentation.
Please
visit
http://www.cypress.com for more information.
3.0
Functional Overview
3.1
USB Signaling Speed
FX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000:
• Full speed, with a signaling bit rate of 12 Mbps
• High speed, with a signaling bit rate of 480 Mbps
FX2 does not support the low-speed signaling mode of 1.5 Mbps.
3.2
8051 Microprocessor
The 8051 microprocessor embedded in the FX2 family has 256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
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