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AT89S53-33PC Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT89S53-33PC Datasheet(HTML) 7 Page - ATMEL Corporation |
7 / 33 page AT89S53 7 SPI Registers Control and status bits for the Serial Periph- eral Interface are contained in registers SPCR (shown in Table 4) and SPSR (shown in Table 5). The SPI data bits are contained in the SPDR register. Writing the SPI data register during serial data transfer sets the Write Collision bit, WCOL, in the SPSR register. The SPDR is double buff- ered for writing and the values in SPDR are not changed by Reset. Interrupt Registers The global interrupt enable bit and the individual interrupt enable bits are in the IE register. In addition, the individual interrupt enable bit for the SPI is in the SPCR register. Two priorities can be set for each of the six interrupt sources in the IP register. Dual Data Pointer Registers To facilitate accessing exter- nal data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WCON selects DP0 and DPS = 1 selects DP1. The user should always initalize the DPS bit to the appropriate value before accessing the respective Data Pointer register. Power Off Flag The Power Off Flag (POF) is located at bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and reset under software control and is not affected by RESET. Table 3. WCON—Watchdog Control Register WCON Address = 96H Reset Value = 0000 0010B PS2 PS1 PS0 reserved reserved DPS WDTRST WDTEN Bit 765 43210 Symbol Function PS2 PS1 PS0 Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of 16 ms. When all three bits are set to “1”, the nominal period is 2048 ms. DPS Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the second bank, DP1 WDTRST Watchdog Timer Reset. Each time this bit is set to “1” by user software, a pulse is generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle. The WDTRST bit is Write-Only. WDTEN Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer. |
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