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AT89C2051 Datasheet(PDF) 11 Page - ATMEL Corporation |
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AT89C2051 Datasheet(HTML) 11 Page - ATMEL Corporation |
11 / 15 page AT89C2051 11 () Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms (1) Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V IH min. for a logic 1 and VIL max. for a logic 0. Float Waveforms (1) Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change frothe loaded VOH/VOL level occurs. Serial Port Timing: Shift Register Mode Test Conditions V CC = 5.0V ± 20%; Load Capacitance = 80 pF Symbol Parameter 12 MHz Osc Variable Oscillator Units Min Max Min Max tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs t QVXH Output Data Setup to Clock Rising Edge 700 10t CLCL-133 ns t XHQX Output Data Hold after Clock Rising Edge 50 2t CLCL-117 ns tXHDX Input Data Hold after Clock Rising Edge 0 0 ns t XHDV Clock Rising Edge to Input Data Valid 700 10t CLCL-133 ns |
Similar Part No. - AT89C2051_00 |
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Similar Description - AT89C2051_00 |
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