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ADUM5401CRWZ1 Datasheet(PDF) 3 Page - Analog Devices |
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ADUM5401CRWZ1 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 24 page  ADuM5401/ADuM5402/ADuM5403/ADuM5404 Rev. 0 | Page 3 of 24 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY 4.5 V ≤ VDD1 ≤ 5.5 V, VSEL = VISO; all voltages are relative to their respective ground. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5.0 V, VSEL = VISO = 5.0 V. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC-TO-DC CONVERTER POWER SUPPLY Setpoint VISO 4.7 5.0 5.4 V IISO = 0 mA Line Regulation VISO(LINE) 1 mV/V IISO = 50 mA, VDD1 = 4.5 V to 5.5 V Load Regulation VISO(LOAD) 1 5 % IISO = 10 mA to 90 mA Output Ripple VISO(RIP) 75 mV p-p 20 MHz bandwidth, CBO = 0.1 μF ║10 μF, IISO = 90 mA Output Noise VISO(N) 200 mV p-p 20 MHz bandwidth, CBO = 0.1 μF ║10 μF, IISO = 90 mA Switching Frequency fOSC 180 MHz Pulse-Width Modulation Frequency fPWM 625 kHz iCoupler DATA CHANNELS DC to 2 Mbps Data Rate1 Maximum Output Supply Current2 IISO(MAX) 100 mA f ≤ 1 MHz, VISO > 4.5 V Efficiency at Maximum Output Supply Current3 34 % IISO = IISO(2,MAX), f ≤ 1 MHz IDD1 Supply Current, No VISO Load IDD1(Q) 19 30 mA IISO = 0 mA, f ≤ 1 MHz 25 Mbps Data Rate (CRWZ Grade Only) IDD1 Supply Current, No VISO Load IDD1(D) ADuM5401 68 mA IISO = 0 mA, CL = 15 pF, f = 12.5 MHz ADuM5402 71 mA IISO = 0 mA, CL = 15 pF, f = 12.5 MHz ADuM5403 75 mA IISO = 0 mA, CL = 15 pF, f = 12.5 MHz ADuM5404 78 mA IISO = 0 mA, CL = 15 pF, f = 12.5 MHz Available VISO Supply Current4 IISO(LOAD) ADuM5401 87 mA CL = 15 pF, f = 12.5 MHz ADuM5402 85 mA CL = 15 pF, f = 12.5 MHz ADuM5403 83 mA CL = 15 pF, f = 12.5 MHz ADuM5404 81 mA CL = 15 pF, f = 12.5 MHz IDD1 Supply Current, Full VISO Load IDD1(MAX) 290 mA CL = 0 pF, f = 0 MHz, VDD = 5 V, IISO = 100 mA I/O Input Currents IIA, IIB, IIC, IID −20 +0.01 +20 μA Logic High Input Threshold VIH 0.7 × VISO, 0.7 × VIDD1 V Logic Low Input Threshold VIL 0.3 × VISO, 0.3 × VIDD1 V Logic High Output Voltages VOAH, VOBH, VOCH, VODH VDD1 − 0.3, VISO − 0.3 5.0 V IOx = −20 μA, VIx = VIxH VDD1 − 0.5, VISO − 0.3 4.8 V IOx = −4 mA, VIx = VIxH Logic Low Output Voltages VOAL, VOBL, VOCL, VODL 0.0 0.1 V IOx = 20 μA, VIx = VIxL 0.0 0.4 V IOx = 4 mA, VIx = VIxL AC SPECIFICATIONS ADuM5401ARWZ/ADuM5402ARWZ/ ADuM5403ARWZ/ADuM5404ARWZ Minimum Pulse Width PW 1000 ns CL = 15 pF, CMOS signal levels Maximum Data Rate 1 Mbps CL = 15 pF, CMOS signal levels Propagation Delay tPHL, tPLH 55 100 ns CL = 15 pF, CMOS signal levels Pulse Width Distortion, |tPLH − tPHL| PWD 40 ns CL = 15 pF, CMOS signal levels Propagation Delay Skew tPSK 50 ns CL = 15 pF, CMOS signal levels Channel-to-Channel Matching tPSKCD/tPSKOD 50 ns CL = 15 pF, CMOS signal levels |
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