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EVAL-CED1Z Datasheet(PDF) 6 Page - Analog Devices |
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EVAL-CED1Z Datasheet(HTML) 6 Page - Analog Devices |
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6 / 32 page  AD7264 Rev. A | Page 6 of 32 TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VREF = 2.5 V internal/external; TA = TMIN to TMAX, unless otherwise noted.1 Table 2. Limit at TMIN, TMAX Parameter 2.7 V ≤ VDRIVE ≤ 3.6 V 4.75 V ≤ VDRIVE ≤ 5.25 V Unit Description fSCLK 200 200 kHz min 34 342 MHz max AD7264 20 20 MHz max AD7264-5 tCONVERT 19 × tSCLK 19 × tSCLK ns max tSCLK = 1/fSCLK 560 560 ns max AD7264 950 950 ns max AD7264-5 tQUIET 13 13 ns min Minimum time between end of serial read/bus relinquish and next falling edge of CS t2 10 10 ns min CS to SCLK setup time t33 15 15 ns max Delay from 19th SCLK falling edge until DOUTA and DOUTB are three-state disabled t4 29 23 ns max Data access time after SCLK falling edge t5 15 13 ns min SCLK to data valid hold time t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t8 13 13 ns min CS rising edge to falling edge pulse width t9 13 13 ns max CS rising edge to DOUTA, DOUTB high impedance/bus relinquish t10 5 5 ns min SCLK falling edge to DOUTA, DOUTB high impedance 35 35 ns max SCLK falling edge to DOUTA, DOUTB high impedance t11 2 2 μs min Minimum CAL pin high time t12 2 2 μs min Minimum time between the CAL pin high and the CS falling edge t13 3 3 ns min DIN setup time prior to SCLK falling edge t14 3 3 ns min DIN hold time after SCLK falling edge tPOWER-UP 240 240 μs max Internal reference, with a 1 μF decoupling capacitor 15 15 μs max With an external reference, 10 μs typical 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Terminology section. 2 The AD7264 is functional with a 40 MHz SCLK at 25°C, but specified performance is not guaranteed with SCLK frequencies greater than 34 MHz. 3 The time required for the output to cross 0.4 V or 2.4 V. CS SCLK 15 19 DOUTA THREE-STATE t4 23 4 20 t5 THREE- STATE t7 t3 18 DB11A DB12A DB13A 21 31 32 33 DB1A DB0A DOUTB THREE-STATE THREE- STATE DB11B DB12B DB13B DB1B DB0B t2 t9 t8 tQUIET t6 Figure 2. Serial Interface Timing Diagram |
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