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AD9388A Datasheet(PDF) 11 Page - Analog Devices |
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AD9388A Datasheet(HTML) 11 Page - Analog Devices |
11 / 28 page AD9388A Rev. B | Page 11 of 28 Pin No. Mnemonic Type1 Description 24 to 33, 36 to 47, 52 to 55, 58 to 61 P0 to P29 O Video Pixel Output Port. 19 INT1 O Interrupt. Can be active low or active high. The set of events that triggers an interrupt is under user control. 20 SYNC_OUT/INT2 O Sliced Synchronization Output Signal (SYNC_OUT). Interrupt Signal (INT2). 17 HS/CS O Horizontal Synchronization Output Signal (HS). Composite Synchronization (CS). A single signal containing both horizontal and vertical synchronization pulses. 18 VS/FIELD O Vertical Synchronization Output Signal (VS). Field Synchronization (FIELD). Field synchronization output signal in all interlaced video modes. 16 DE/FIELD O Data Enable Signal (DE). Indicates active pixel data. Field Synchronization (FIELD). Field synchronization output signal in all interlaced video modes. 11 SDA I/O I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. 12 SCL I I2C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is the clock line for the control port. 13 ALSB I This pin sets the second LSB of each AD9388A register map. 21 RESET I System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the AD9388A circuitry. 51 LLC O Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz. 65 XTAL1 O This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external 3.3 V 28.63636 MHz clock oscillator source is used to clock the AD9388A. In crystal mode, the crystal must be a fundamental crystal. 66 XTAL I Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3.3 V 28.63636 MHz clock oscillator source to clock the AD9388A. 70 ELPF O The recommended external loop filter must be connected to this ELPF pin. 102 AUDIO_ELPF O The recommended external loop filter must be connected to this AUDIO_ELPF pin. 85 REFOUT O Internal Voltage Reference Output. 86 CML O Common-Mode Level for the Internal ADCs. 90 REFN I Internal Voltage Output. 92 REFP I Internal Voltage Output. 63 HS_IN/CS_IN I HS Input Signal. Used in analog mode for 5-wire timing mode. CS Input Signal. Used in analog mode for 4-wire timing mode. For optimal performance, a 100 Ω series resistor is recommended on the HS_IN/CS_IN pin. 62 VS_IN I VS Input Signal. This pin is used in analog mode for 5-wire timing mode. For optimal performance, a 100 Ω series resistor is recommended on the VS_IN pin. 75 SOG I Synchronization-on-Green Input. This pin is used in embedded synchronization mode. 97 SOY I Synchronization-on-Luma Input. This pin is used in embedded synchronization mode. 112 RXA_CN I Digital Input Clock Complement of Port A in the HDMI Interface. 113 RXA_CP I Digital Input Clock True of Port A in the HDMI Interface. 115 RXA_0N I Digital Input Channel 0 Complement of Port A in the HDMI Interface. 116 RXA_0P I Digital Input Channel 0 True of Port A in the HDMI Interface. 118 RXA_1N I Digital Input Channel 1 Complement of Port A in the HDMI Interface. 119 RXA_1P I Digital Input Channel 1 True of Port A in the HDMI Interface. |
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