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ONET1101LRGET Datasheet(PDF) 6 Page - Texas Instruments |
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ONET1101LRGET Datasheet(HTML) 6 Page - Texas Instruments |
6 / 26 page www.ti.com AC ELECTRICAL CHARACTERISTICS DETAILED DESCRIPTION EQUALIZER LIMITER HIGH-SPEED OUTPUT DRIVER ONET1101L SLLS883 – MARCH 2008 Over recommended operating conditions with 25 Ω output load, open loop operation, IMOD = 40 mA, IBIAS = 40 mA, and RRZTC = 28.7 kΩ. Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SDD11 0.01 GHz < f < 3.9 GHz –16 Differential input return gain dB 3.9 GHz < f < 12.1 GHz See note(1) SCD11 f < 8.25 GHz –45 Differential to common mode dB conversion gain 8.25 GHz < f < 20 GHz –35 tR-OUT Output rise time 20% to 80%, tR-IN < 40 ps, 25 Ω load, single-ended 25 35 ps tF-OUT Output fall time 20% to 80%, tF-IN < 40 ps, 25 Ω load, single-ended 25 35 ps IMOD-MIN Minimum modulation current 10 mA IMOD-MAX Maximum modulation current AC Coupled Outputs 70 85 mA IMOD-STEP Modulation current step size 10 Bit Register 83 µA EQENA = 0, K28.5 pattern at 11.3 Gbps, 100 mVpp, 5 10 600 mVpp, 1200 mVpp differential input voltage DJ Deterministic output jitter psp-p EQENA = 1, K28.5 pattern at 11.3 Gbps, maximum equalization with 12” transmission line at the input, 400 7 mVpp at input to transmission line RJ Random output jitter 0.4 0.8 psRMS CAPC = 0.01 µF, IPD = 100 µA, τ APC APC time constant 120 µs PD coupling ratio, CR = 40(2) Cross Point Control Range 30% 70% TOFF Transmitter disable time Rising edge of DIS to IBIAS ≤ 0.1 × IBIAS-NOMINAL (2) 0.05 5 µs TON Disable negate time Falling edge of DIS to IBIAS ≥ 0.9 × IBIAS-NOMINAL (2) 1 ms TINIT1 Power-on to initialize Power-on to registers ready to be loaded 1 10 ms TINIT2 Initialize to transmit Register load STOP command to part ready to transmit 2 ms valid data(2) TRESET DIS pulse width Time DIS must be held high to reset part(2) 100 ns TFAULT Fault assert time Time from fault condition to FLT high(2) 50 µs (1) Differential Return Gain given by SDD11, SDD22 = –11.6 + 13.33 × log 10(f÷8.25), f expressed in GHz (2) Assured by simulation over process, supply, and temperature variation. The data signal can be applied to an input equalizer by means of the input signal pins DIN+ / DIN–, which provide on-chip differential 100 Ω line-termination. The equalizer is enabled by setting EQENA = 1 (bit 1 of register 0). Equalization of up to 300 mm (12") of microstrip or stripline transmission line on FR4 printed circuit boards can be achieved. The amount of equalization is digitally controlled by the two-wire interface and control logic block, and is dependant on the register settings EQADJ[0...7] (register 6). The equalizer can also be turned off and bypassed by setting EQENA = 0. For details about the equalizer settings, see Table 12 - Register Functionality. By limiting the output signal of the equalizer to a fixed value, the limiter removes any overshoot after the input equalization and provides the input signal for the output driver. The modulation current is sunk from the common emitter node of the limiting output driver differential pair by means of a modulation current generator, which is digitally controlled by the 2-wire serial interface. 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :ONET1101L |
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