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ONET1101LRGERG4 Datasheet(PDF) 9 Page - Texas Instruments |
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ONET1101LRGERG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 26 page www.ti.com P S S P SDA SCK t BUF t LOW t SUSTA t HIGH t HDSTA t r t HDSTA t HDSTA t SUDAT t SUSTO t f T0295-01 S SDA SCK P 1–7 1–7 1–7 SLAVE ADDRESS R/W ACK 8 9 8 9 REGISTER ADDRESS ACK 8 9 ACK REGISTER FUNCTION T0296-01 REGISTER MAPPING ONET1101L SLLS883 – MARCH 2008 Figure 2. I2C Timing Diagram Table 1. Timing Diagram Definitions PARAMETER MIN MAX UNIT fSCK SCK clock frequency 400 kHz tBUF Bus free time between START and STOP conditions 1.3 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.6 µs tLOW Low period of the SCK clock 1.3 µs tHIGH High period of the SCK clock 0.6 µs tSUSTA Setup time for a repeated START condition 0.6 µs tHDDAT Data HOLD time 0 µs tSUDAT Data setup time 100 ns tR Rise time of both SDA and SCK signals 300 ns tF Fall time of both SDA and SCK signals 300 ns tSUSTO Setup time for STOP condition 0.6 µs Figure 3. I2C Data Transfer The register mapping for register addresses 0 (0x00) through 9 (0x09) are shown in Table 2 through Table 11. Table 12 describes the circuit functionality based on the register settings. Table 2. Register 0 (0x00) Mapping – Control Settings register address 0 (0x00) bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0 ENA PDRNG1 PDRNG0 OLENA FLTEN POL EQENA PDPOL Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s) :ONET1101L |
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