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ADS62P43IRGCRG4 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS62P43IRGCRG4 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 70 page  www.ti.com TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) ADS62P45, ADS62P44 ADS62P43, ADS62P42 SLAS561A – JULY 2007 – REVISED FEBRUARY 2008 Typical values are specified at 25 °C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), I O = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V, unless otherwise specified. ADS62P45 ADS62P44 ADS62P43 ADS62P42 FS = 125 MSPS FS = 105 MSPS FS = 80 MSPS FS = 65 MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Aperture ta 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 0.7 1.5 2.5 ns delay Aperture channel-to-channel delay within the same device ±80 ±80 ±80 ±80 ps variation Aperture tj 150 150 150 150 fs rms jitter from global power 15 50 15 50 15 50 15 50 µs down Wake-up time from standby 15 50 15 50 15 50 15 50 µs (to valid from output CMOS 100 200 100 200 100 200 100 200 ns data) buffer LVDS 200 500 200 500 200 500 200 500 ns disable clock default, after reset 14 14 14 14 cycles with low latency mode clock Latency 10 10 10 10 enabled cycles with decimation filter clock 15 15 15 15 enabled cycles DDR LVDS MODE(4), DRVDD = 3.0 V to 3.6 V Data valid (6) to Data setup tsu zero-cross of 0.6 1.5 1.0 2.3 2.4 3.8 3.8 5.2 ns time(5) CLKOUTP Zero-cross of Data hold th CLKOUTP to data 1.0 2.3 1.0 2.3 1.0 2.3 1.0 2.3 ns time(5) becoming invalid(6) Input clock rising edge Clock zero-cross to output tPDI propagation 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 7.5 3.5 5.5 7.5 ns clock rising edge delay zero-cross Duty cycle of LVDS bit differential clock, clock duty (CLKOUTP- 46% 50% 53% 46% 50% 53% 46% 50% 53% 46% 50% 53% cycle CLKOUTM) 10 ≤ Fs ≤ 125 MSPS Rise time measured Data rise from –50 mV to 50 mV tr time Fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps tf Data fall from 50 mV to –50 mV time 1 ≤ Fs ≤ 125 MSPS Rise time measured tCLKRI Output clock from –50 mV to 50 mV SE rise time Fall time measured 70 100 170 70 100 170 70 100 170 70 100 170 ps tCLKFA Output clock from 50 mV to –50 mV LL fall time 1 ≤ Fs ≤ 125 MSPS PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.6 V, default output buffer drive strength (7) Data setup Data valid(8) to 50% of tsu 2.0 3.5 2.8 4.3 4.3 5.8 5.7 7.2 ns time(5) CLKOUT rising edge (1) Timing parameters are specified by design and characterization and not tested in production. (2) CL is the effective external single-ended load capacitance between each output pin and ground. (3) IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. (4) Measurements are done with a transmission line of 100- Ω characteristic impedance between the device and the load. (5) Setup and hold time specifications take into account the effect of jitter on the output data and clock. (6) Data valid refers to logic high of +100 mV and logic low of –100 mV. (7) For DRVDD < 2.2 V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See Parallel CMOS interface in application section. (8) Data valid refers to logic high of 2 V (1.7 V) and logic low of 0.8 V (0.7 V) for DRVDD = 3.3 V (2.5 V). 8 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42 |
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