AZ62P44 datasheet(9/70 Pages) TI

Part #	AZ62P44

Description	DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

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ADS62P45, ADS62P44

ADS62P43, ADS62P42

SLAS561A – JULY 2007 – REVISED FEBRUARY 2008

TIMING CHARACTERISTICS – LVDS AND CMOS MODES (continued)

Typical values are specified at 25

°C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock,

1.5 VPP clock amplitude, CL = 5 pF, IO = 3.5 mA, RL = 100 Ω, no internal termination, unless otherwise noted.

Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V,

unless otherwise specified.

ADS62P45

ADS62P44

ADS62P43

ADS62P42

FS = 125 MSPS

FS = 105 MSPS

FS = 80 MSPS

FS = 65 MSPS

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

50% of CLKOUT rising

Data hold

th

edge to data becoming

2.0

3.5

2.7

4.2

5.7

5.6

7.1

ns

time(5)

invalid(8)

Clock

Input clock rising edge

tPDI

propagation

zero-cross to 50% of

5.8

7.3

8.8

5.8

7.3

8.8

5.8

7.3

8.8

5.8

7.3

8.8

ns

delay

CLKOUT rising edge

Duty cycle of output

Output clock

clock (CLKOUT)

45%

53%

60%

45%

53%

60%

45%

53%

60%

45%

53%

60%

duty cycle

10

≤ Fs ≤ 125 MSPS

Rise time measured

from 20% to 80% of

Data rise

DRVDD

tr

time

Fall time measured

1.0

1.8

2.5

1.0

1.8

2.5

1.0

1.8

2.5

1.0

1.8

2.5

ns

tf

Data fall

from 80% to 20% of

time

DRVDD

1

≤ Fs ≤ 125 MSPS

Rise time measured

from 20% to 80% of

tCLKRI

Output clock

DRVDD

SE

rise time

Fall time measured

1.0

1.8

2.5

1.0

1.8

2.5

1.0

1.8

2.5

1.0

1.8

2.5

ns

tCLKFA

Output clock

from 80% to 20% of

LL

fall time

DRVDD

1

≤ Fs ≤ 125 MSPS

Timing Characteristics at Lower Sampling Frequencies

Sampling

tPDI CLOCK PROPAGATION DELAY,

frequency,

tsu DATA SETUP TIME, ns

th DATA HOLD TIME, ns

ns

MSPS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

CMOS INTERFACE, DRVDD = 2.5 V TO 3.6 V

40

10.5

12

10.3

11.8

5.8

7.3

8.8

20

23

24.5

23

24.5

LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V

40

8.5

10

1

2.3

3.5

5.5

7.5

20

21

22.5

1

2.3

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Product Folder Link(s): ADS62P45, ADS62P44 ADS62P43, ADS62P42

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