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TPS720 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS720 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 19 page DEVICE INFORMATION Thermal Shutdown Current Limit UVLO Bandgap IN EN OUT BIAS PIN CONFIGURATION BIAS IN EN GND OUT C3 B2 A3 C1 A1 TPS720xx TPS720xx www.ti.com ............................................................................................................................................................. SBVS100A – JUNE 2008 – REVISED JUNE 2008 Functional Block Diagram YZU PACKAGE WCSP-5 (TOP VIEW) PIN DESCRIPTIONS TPS720xx NAME YZU DESCRIPTION Input pin. This pin can be a maximum of 4.5V; VIN must not exceed VBIAS. Bypass this input with a ceramic IN A1 capacitor to ground. Output pin. A 2.2 µF ceramic capacitor is connected from this pin to ground, for stability and to provide load OUT A3 transients. GND B2 Ground pin. Bias supply pin. It is recommended that this input be bypassed with a ceramic capacitor to ground for better BIAS C1 transient performance. Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to OUT. A logic low EN C3 on this pin turns off the device. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5 |
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