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EMC326SP16AJV-90L Datasheet(PDF) 3 Page - Emerging Memory & Logic Solutions Inc |
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EMC326SP16AJV-90L Datasheet(HTML) 3 Page - Emerging Memory & Logic Solutions Inc |
3 / 64 page EMC326SP16AJ 2Mx16 CellularRAM 3 Preliminary Table of Contents Features ................................................................................................................................................................................. 2 Options ............................................................................................................................................................................... 2 General Description ................................................................................................................................................................ 6 Functional Description ............................................................................................................................................................ 9 Power-Up Initialization ....................................................................................................................................................... 9 Bus Operating Modes ............................................................................................................................................................. 10 Asynchronous Mode .......................................................................................................................................................... 10 Page Mode READ Operation ............................................................................................................................................ 11 Burst Mode Operation ........................................................................................................................................................ 12 Mixed-Mode Operation ....................................................................................................................................................... 15 WAIT Operation ................................................................................................................................................................. 15 LB# / UB# Operation........................................................................................................................................................... 15 Low-Power Operation......... .................................................................................................................................................... 16 Standby Mode Operation ................................................................................................................................................... 16 Temperature Compensated Refresh................................................................................................................................... 16 Partial Array Refresh .......................................................................................................................................................... 16 Deep Power-Down Operation............................................................................................................................................. 16 Registers................................................................................................................................................................................. 17 Access Using CRE ............................................................................................................................................................. 17 Software Access ................................................................................................................................................................ 21 Bus Configuration Register................................................................................................................................................. 22 Burst Length (BCR[2:0]) Default = Continuous Burst ..................................................................................................... 23 Burst Wrap (BCR[3]) Default = No Wrap ........................................................................................................................ 23 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ........................................................................... 24 WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid / Invalid................................... 24 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH................................................................................................... 24 Latency Counter (BCR[13:11]) Default = Three Clock Latency .................................................................................... 25 Initial Access Latency (BCR[14]) Default = Variable....................................................................................................... 25 Operating Mode (BCR[15]) Default = Asynchronous Operation..................................................................................... 26 Refresh Configuration Register........................................................................................................................................... 27 Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh ..................................................................................... 28 Deep Power-Down (RCR[4]) Default = DPD Disabled ................................................................................................... 28 Page Mode Operation (RCR[7]) Default = Disabled ...................................................................................................... 28 Device Identification Register.............................................................................................................................................. 28 Electrical Characteristics......................................................................................................................................................... 29 Timing Requirements.............................................................................................................................................................. 31 Timing Diagrams..................................................................................................................................................................... 35 |
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