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EM742SP16C-12LL Datasheet(PDF) 8 Page - Emerging Memory & Logic Solutions Inc |
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EM742SP16C-12LL Datasheet(HTML) 8 Page - Emerging Memory & Logic Solutions Inc |
8 / 10 page EM742SP16 256Kx16 Multiplexed STRAM 8 TIMING WAVEFORM OF WRITE CYCLE (2) (OE = VIH) Write Access The write access is initiated by applying the address to the multiplexed address/data bus or to the address bus over A15 (A16 -> Axx). When the address is stable, the device chip select(CS) is set active low. At point A, the AVD signal is taken low and the latch becomes transparent. This allows the address to be propagated to the memory array. The address is stable at the rising edge of the AVD signal. The AVD signal goes high at point B in which the address latch is completed. At this point, the second stage of the write process is entered. Data is input to the multiplexed address/data bus. The WE signal is set low and control signal UB and LB are set according to the access. tAVD tAVDS tAVDH Address Valid Data Valid tDH tACW2 tCSS tBW C B A AVD WE CS UB, LB Address/Data tDW tWRL TIMING WAVEFORM OF WRITE CYCLE (1) (OE = VIH) tAVD tACW1 tAVDS tAVDH Address Valid Data Valid tDH tACW2 tCSS tACW3 tBW C B A AVD WE CS UB, LB Address/Data tDW tWRL NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWRL) of low CS, low WE and low UB or LB. A write begins at the last transition among low CS and low WE with asserting UB or LB low for single byte operation or simultaneously asserting UB and LB low for word operation. A write ends at the earliest transition among high CS and high WE. The tWRL is measured from the beginning of write to the end of write. |
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