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EMP116MEAW-70E Datasheet(PDF) 6 Page - Emerging Memory & Logic Solutions Inc |
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EMP116MEAW-70E Datasheet(HTML) 6 Page - Emerging Memory & Logic Solutions Inc |
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6 / 14 page  EMP116MEAW Series 1Mx16 Pseudo Static RAM Preliminary Rev 0.0 AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.2V to VCCQ-0.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : VCCQ/2 Output Load (See right) : CL1) = 30pF 1. Including scope and Jig capacitance CL1) AC CHARACTERISTICS (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = -25C to +85oC) Dout Parameter List Symbol Speed Unit Min Max Read Read Cycle Time tRC 70 1k ns Address access time tAA - 70 ns Chip enable to data output tCO - 70 ns Output enable to valid output tOE - 25 ns UB#, LB# enable to data output tBA - 70 ns Chip enable to low-Z output tLZ 10 - ns UB#, LB# enable to low-Z output tBLZ 10 - ns Output enable to low-Z output tOLZ 5 - ns Chip disable to high-Z output tHZ 0 15 ns UB#, LB# disable to high-Z output tBHZ 0 15 ns Output disable to high-Z output tOHZ 0 15 ns Output hold from Address change tOH 5 - ns Write Write Cycle Time tWC 70 1k ns Chip enable to end of write tCW 60 - ns Address setup time tAS 0 - ns Address valid to end of write tAW 60 - ns UB#, LB# valid to end of write tBW 60 - ns Write pulse width tWP 50 - ns Write recovery time tWR 0 - ns Write to output high-Z tWHZ 0 15 ns Data to write time overlap tDW 20 - ns Data hold from write time tDH 0 - ns End write to output low-Z tOW 5 - ns Page Maximum cycle time tMRC - 1k ns Page mode cycle time tPC 25 - ns Page mode address access time tPAA - 25 ns |
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