EM7323SU16H

2Mx16 Async. / Page StRAM

10

Preliminary

Rev. 0.0

Notes :

1. Stresses greater than listed under “Absolute Maximum Ratings” may cause permanet damage to the device.

2. All voltages are reference to VSS.

3. IDD0 depends on the cycle time.

4. IDD0 depends on output loading. Specified values are defined with the output open condition.

5. AC measurement are assumed tR, tF = 5ns.

6. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not

output voltage reference levels

7. Data cannot be retained at deep power-down stand-by mode.

8. If OE is high during the write cycle, the outputs will remain at high impedence.

9. During the output state of DQ signals, input signals of reverse polarity must not be applied.

10. If CE1 or LB / UB goes LOW coincident with or after WE goes LOW, the outputs will remain at high impedence.

11. If CE1 or LB./UB goes HIGH coincident with or before WE goes HIGH, the outputs will remain at high impedence.