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RMS132UAW-6E Datasheet(PDF) 6 Page - Emerging Memory & Logic Solutions Inc |
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RMS132UAW-6E Datasheet(HTML) 6 Page - Emerging Memory & Logic Solutions Inc |
6 / 26 page Advance Information The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. 6 RMS132UAW WB Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 4. Table 4: Burst Definition Burst Read and Single Write 1 Burst Read and Burst Write 0 Write Burst Mode M9 Interleave 1 Sequential 0 Burst Type M3 Reserved 0 0 1 Reserved 1 0 1 2 0 1 0 - 1 0 0 3 1 1 0 Reserved 0 1 1 Reserved 1 1 1 Reserved 0 0 0 CAS Latency M4 M5 M6 Full Page Reserved Reserved Reserved 8 4 2 1 M3 = 0 Burst Length Reserved 0 0 1 Reserved 1 0 1 4 0 1 0 2 1 0 0 8 1 1 0 Reserved 0 1 1 Reserved 1 1 1 1 0 0 0 M3 = 1 M0 M1 M2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 A0 A1 A2 7-6-5-4-3-2-1-0 7-0-1-2-3-4-5-6 1 8 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-0 0 2-3-0-1-6-7-4-5 2-3-4-5-6-7-0-1 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 5-4-7-6-1-0-3-2 5-6-7-0-1-2-3-4 1 1-0-3-2 1-2-3-0 2-3-0-1 2-3-0-1 3-2-1-0 3-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-0-1-2 0 4 0-1-2-3 0-1-2-3 0-1 0-1 2 1-0 1-0 6-7-4-5-2-3-0-1 6-7-0-1-2-3-4-5 1 Not Supported C n, Cn+1. Cn+2, C n+3, Cn+4… …C n-1, Cn... n=A0-7 (Location 0-256) Full Page Interleaved Sequential Order of Access Within a Burst Starting Column Address Burst Length Note : 1. For full-page accesses: y = 256 2. For a burst length of two, A1-A7 select the block- of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A7 select the block- of-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A7 select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A7 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A7 select the unique column to be accessed, and mode register bit M3 is ignored. 0 CAS Latency BT Burst Length Address Bus 0 1 2 3 4 5 6 10 987 11 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA Mode Register (Mx) 00 0 Figure4: Mode Register Definition Note: M11(BA) must be set to “0” to select Mode Register (vs. the Extended Mode Register) |
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