EMC646SP16K

4Mx16 CellularRAM AD-MUX

10

Preliminary

BUS OPERATING MODES

64M CelluarRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This

bus interface supports asynchronous and burst mode read and write transfers. The specific interface supported is defined by the value

loaded into the BCR.

Asynchronous Mode

Asynchronous mode uses the industry- standard SRAM control signals (CE#, ADV#, OE#, WE#, and LB#/UB#). READ operations(Fig-

ure 3 on page 11) are initiated by bringing CE#, ADV#, and LB#/UB# LOW while keeping OE# and WE# HIGH, and driving the address

onto the A/DQ bus. ADV# is taken HIGH to capture the address, and OE# is taken LOW. Valid data will be driven out of the I/Os after the

specified access time has elapsed. WRITE operations(Figure 4 on page 11) occur when CE#, ADV#, WE#, and LB#/UB# are driven

LOW. with the address on the A/DQ bus. ADV# is taken HIGH to capture the address, then the WRITE data is driven onto the bus. Dur-

ing asynchronous WRITE operations, the OE# level is a “Don't Care,” and WE# will override OE#; however, OE# must be HIGH while

the address is driven onto the A/DQ bus. The data to be written is latched on the rising edge of CE#, WE#, UB#, or LB# (whichever

occurs first). During asynchronous operations with burst mode enabled, the CLK input must be held static(HIGH or LOW). WAIT will be

driven during asynchronous READs, and its state should be ignored. WE# LOW time must be limited to tCEM.