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EMD12324P-75 Datasheet(PDF) 7 Page - Emerging Memory & Logic Solutions Inc |
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EMD12324P-75 Datasheet(HTML) 7 Page - Emerging Memory & Logic Solutions Inc |
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7 / 44 page  7 EMD12324P 512M: 16M x 32 Mobile DDR SDRAM Rev 0.0 Preliminary Table 6: DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85 ) Parameter Symbol Test Condition Version Unit -60 -75 Operating one bank active-precharge current IDD0 tRC = tRCmin; tCK = tCKmin; CKE is HIGH; CSB is HIGH between valid commands; address inputs are SWITCH- ING; data bus inputs are STABLE 100 80 mA Precharge power-down standby current IDD2P all banks idle, CKE is LOW; CSB is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 0.6 mA Precharge power-down standby current with clock stop IDD2PS all banks idle, CKE is LOW; CSB is HIGH, CK = LOW, CKB = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 0.6 Precharge non power- down standby current IDD2N all banks idle, CKE is HIGH; CSB is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 25 20 mA Precharge non power- down standby current with clock stop IDD2NS all banks idle, CKE is HIGH; CSB is HIGH, CK = LOW, CKB = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 5 5 Active power-down standby current IDD3P one bank active, CKE is LOW; CSB is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 8 mA Active power-down standby current with clock stop IDD3PS one bank active, CKE is LOW; CSB is HIGH, CK = LOW, CKB = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 5 Active non power-down standby current IDD3N one bank active, CKE is HIGH; CSB is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 25 25 mA Active non power-down standby current with clock stop IDD3NS one bank active, CKE is HIGH; CSB is HIGH, CK = LOW, CKB = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 10 10 mA Operating burst read current IDD4R one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; Iout = 0 mA; address inputs are SWITCHING; 50% data change each burst transfer 160 130 mA Operating burst write current IDD4W one bank active; tCK = tCKmin; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer 130 105 mA Auto-Refresh current IDD5 tRC = tRFCmin; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 120 120 mA Self Refresh Current IDD6 CKE is LOW, CK = LOW, CKB = HIGH; Extended Mode Reg- ister set to all 0s; address and control inputs are STABLE; data bus inputs are STABLE TCSR Range 45*1 85 °C Full Array 350 600 µA 1/2 of Full Array 250 500 1/4 of Full Array 200 450 Deep Power-Down Current IDD8 Address and Control inputs are STABLE; data bus inputs are STABLE 10 10 µA |
Similar Part No. - EMD12324P-75 |
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Similar Description - EMD12324P-75 |
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