2

EMD28164PA

128M: 8M x 16 Mobile DDR SDRAM

Rev 1.0

128M : 8M x 16bit Mobile DDR SDRAM

Table 1: ORDERING INFORMATION

NOTE :

1. EMLSI is not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.

Please contact to the memory marketing team in EMLSI when considering the use of a product contained herein for any specific purpose,

such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.

Part No.

Max Freq.

Interface

Package

Remark

EMD28164PA-60(DDR333)

166㎒(CL3), 111㎒(CL2)

LVCMOS

Wafer Biz.

EMD28164PA-75(DDR266)

133㎒(CL3), 83㎒(CL2)

EMD28164PA-90(DDR222)

111㎒(CL3), 66㎒(CL2)

FEATURES

· 1.8V power supply, 1.8V I/O power

· LVCMOS compatible with multiplexed address.

· Double-data-rate architecture; two data transfers per clock

cycle

· Bidirectional data strobe(DQS)

· Four banks operation.

· MRS cycle with address key programs.

· CAS latency (2, 3 & 4).

· Burst length (2, 4, 8 & 16).

· Burst type (Sequential & Interleave).

· Differential clock inputs(CK and /CK).

· EMRS cycle with address key programs.

· PASR(Partial Array Self Refresh).

· DS (Driver Strength)

· Internal auto TCSR

(Temperature Compensated Self Refresh)

· Deep power-down(DPD) mode.

· DM for write masking only.

· Auto refresh and self refresh modes.

· 64㎳ refresh period (4K cycle).

· Operating temperature range (-25℃ ~ 85℃).

GENERAL DESCRIPTION

This EMD28164PA is 134,217,728 bits synchronous double data

rate Dynamic RAM. Each 33,554,432 bits bank is organized as

4,096 rows by 512 columns by 16 bits, fabricated with EMLSI’s

high performance CMOS technology.

This device uses a double data rate architecture to achieve high-

speed operation. The double data rate architecture is essentially

a 2n-prefetch architecture with an interface designed to transfer

two data words per clock cycle at the I/O balls.

Range of operating frequencies, programmable burst lengths

and programmable latencies allow the same device to be useful

for a variety of high bandwidth and high performance memory

system applications.