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V53C806H45 Datasheet(PDF) 1 Page - Mosel Vitelic, Corp |
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V53C806H45 Datasheet(HTML) 1 Page - Mosel Vitelic, Corp |
1 / 18 page MOSEL VITELIC 1 V53C806H HIGH PERFORMANCE 1M x 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM PRELIMINARY V53C806H Rev. 1.6 April 1998 HIGH PERFORMANCE 40 45 50 60 Max. RAS Access Time, (tRAC) 40 ns 45 ns 50 ns 60 ns Max. Column Address Access Time, (tCAA) 20 ns 22 ns 24 ns 30 ns Min. Fast Page Mode Cycle Time, (tPC) 23 ns 25 ns 28 ns 40 ns Min. Read/Write Cycle Time, (tRC) 75 ns 80 ns 90 ns 120 ns Features s 1M x 8-bit organization s Fast Page Mode for a sustained data rate of 43 MHz s RAS access time: 40, 45, 50, 60 ns s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh capability s Refresh Interval: 1024 cycle/16 ms s Available in 28-pin 400 mil SOJ package s Single +5V ±10% Power Supply s TTL Interface Description The V53C806H is a ultra high speed 1,048,576 x 8 bit CMOS dynamic random access memory. The V53C806H offers a combination of features: Fast Page Mode for high data bandwidth, and Low CMOS standby current. All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Fast Page Mode operation allows random access of up to 1024 x 8 bits within a row with cycle times as fast as 23 ns. Because of static circuitry, the CAS clock is not in the critical timing path. The flow-through col- umn address latches allow address pipelining while relaxing many critical system timing requirements. The V53C806H is ideally suited for graphics, dig- ital signal processing and high-performance com- puting systems. Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Power Temperature Mark K 40 45 50 60 Std. 0 °C to 70 °C • •••• • Blank |
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