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EM625FS8BT-10LL Datasheet(PDF) 5 Page - Emerging Memory & Logic Solutions Inc |
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EM625FS8BT-10LL Datasheet(HTML) 5 Page - Emerging Memory & Logic Solutions Inc |
5 / 11 page EM620FU16B Series Low Power, 128Kx16 SRAM 5 AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4V to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL1) = 100pF + 1 TTL (70ns) CL1) = 30pF + 1 TTL (45ns/55ns) 1. Including scope and Jig capacitance 2. R1=3070 ohm, R2=3150 ohm 3. VTM=2.8V 4. CL = 5pF + 1 TTL (measurement with tLZ1,2, tHZ1,2, tOLZ, tOHZ, tWHZ) CL1) VTM3) R12) R22) Parameter Symbol 45ns 55ns 70ns Unit Min Max Min Max Min Max Read cycle time tRC 45 - 55 - 70 - ns Address access time tAA -45 - 55 - 70 ns Chip select to output tCO1, tCO2 -45 - 55 - 70 ns Output enable to valid output tOE -25 - 25 - 35 ns UB, LB access time tBA 45 55 70 ns Chip select to low-Z output tLZ1, tLZ2 10 - 10 - 10 - ns UB, LB enable to low-Z output tBLZ 5 - 10 - 10 - ns Output enable to low-Z output tOLZ 5-5- 5 - ns Chip disable to high-Z output tHZ1, tHZ2 020020 0 25 ns UB, LB disable to high-Z output tBHZ 015020 0 25 ns Output disable to high-Z output tOHZ 015020 0 25 ns Output hold from address change tOH 10 - 10 - 10 - ns Parameter Symbol 45ns 55ns 70ns Unit Min Max Min Max Min Max Write cycle time tWC 45 - 55 - 70 - ns Chip select to end of write tCW1, tCW2 45 - 45 - 60 - ns Address setup time tAS 0-0- 0 - ns Address valid to end of write tAW 45 - 45 - 60 - ns UB, LB valid to end of write tBW 45 - 45 - 60 - ns Write pulse width tWP 35 - 40 - 50 - ns Write recovery time tWR 0-0- 0 - ns Write to ouput high-Z tWHZ 0 15 0 20020 ns Data to write time overlap tDW 25 25 30 ns Data hold from write time tDH 0-0- 0 - ns End write to output low-Z tOW 5-5- 5 - ns READ CYCLE (Vcc =2.7 to 3.3V, Gnd = 0V, TA = -40oC to +85oC) WRITE CYCLE (Vcc =2.7 to 3.3V, Gnd = 0V, TA = -40oC to +85oC) |
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