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ST95022 Datasheet(PDF) 4 Page - STMicroelectronics |
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ST95022 Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 16 page OPERATIONS All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on the first rising edge of clock (C) after the chip select (S) goes low. Prior to any operation, a one-byte instruction code must be entered in the chip. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been previously selected (S = low). Table 3 shows the instruction set and format for device operation. If an invalid instruction is sent (one not contained in Table 3), the chip is automatically deselected. Write Enable (WREN) and Write Disable (WRDI) The ST95022 contains a write enable latch. This latch must be set prior to every WRITE or WRSR operation. The WREN instruction will set the latch and the WRDI instruction will reset the latch. The latch is reset under the following conditions: – W pin is low – Power on – WRDI instruction executed – WRSR instruction executed – WRITE instruction executed As soon as the WREN or WRDI instruction is received by the ST95022, the circuit executes the instruction and enters a wait mode until it is dese- lected. Read Status Register (RDSR) The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write to the memory operation. As soon as the 8th bit of the status register is read out, the ST95022 enters a wait mode (data on D is not decoded, Q is in Hi-Z) until it is deselected. The status register format is as follows: b7 b0 1 1 1 1 BP1 BP0 WEL WIP BP1, BP0: Read and write bits. WEL, WIP: Read only bits. b7 to b4: Read only bits. During a write to the memory operation to the memory array, all bits BP1, BP0, WEL, WIP are valid and can be read. During a write to the status register, only the bits WEL and WIP are valid and can be read. The values of BP1 and BP0 read at that time correspond to the previous contents of the status register. The Write-In-Process (WIP) read-only bit indicates whether the ST95022 is busy with a write opera- tion. When set to a ’1’ a write is in progress, when set to a ’0’ no write is in progress. The Write Enable Latch (WEL) read-only bit indi- cates the status of the write enable latch. When set to a ’1’ the latch is set, when set to a ’0’ the latch is reset. The Block Protect (BP0 and BP1) bits indi- cate the extent of the protection employed. These bits are set by the user issuing the WRSR instruc- tion. These bits are non-volatile. Write Status Register (WRSR) The WRSR instruction allows the user to select the size of protected memory. The ST95022 is divided into four 512 bit blocks. The user may read the blocks but will be unable to write within the pro- Instruction Description Instruction Format WREN Set Write Enable Latch 0000 0110 WRDI Reset Write Enable Latch 0000 0100 RDSR Read Status Register 0000 0101 WRSR Write Status Register 0000 0001 READ Read Data from Memory Array 0000 0011 WRITE Write Data to Memory Array 0000 0010 Notes: A = 1, Upper page selected A = 0, Lower page selected Table 3. Instruction Set 4/16 ST95022 |
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