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PSD835F2V-A-12U Datasheet(PDF) 11 Page - STMicroelectronics

Part # PSD835F2V-A-12U
Description  Configurable Memory System on a Chip for 8-Bit Microcontrollers
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD835F2V-A-12U Datasheet(HTML) 11 Page - STMicroelectronics

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PSD8XX Family
PSD835G2
10
Pin*
(TQFP
Pin Name Pkg.)
Type
Description
PE3
74
I/O
Port E, PE3. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TDO output for JTAG/ISP interface.
PE4
75
I/O
Port E, PE4. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TSTAT output for the ISP interface.
4. Rdy/Bsy — for in-circuit Parallel Programming.
PE5
76
I/O
Port E, PE5. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. TERR active low output for ISP interface.
PE6
77
I/O
Port E, PE6. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. Vstby — SRAM standby voltage input for battery
backup SRAM
PE7
78
I/O
Port E, PE7. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address output.
3. Vbaton — battery backup indicator output. Goes high when
power is drawn from an external battery.
PF0-PF7
31-38
I/O
Port F, PF0-7. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Input to the PLD.
3. Latched address outputs.
4. As address A0-3 inputs in 80C51XA mode
5. As data bus port (D0-7) in non-multiplexed bus configuration
PG0-PG7 21-28
I/O
Port G, PG0-7. This port is pin configurable and has multiple
CMOS
functions:
or Open
1. MCU I/O — standard output or input port.
Drain
2. Latched address outputs.
GND
8,30,
49,50,
70
VCC
9,29,
69
Table 5.
PSD835G2
Pin
Descriptions
(cont.)


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