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ST6262BM1 Datasheet(PDF) 10 Page - STMicroelectronics |
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ST6262BM1 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 68 page 10/68 ST62T52B ST62T62B/E62B MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM Bank Register (DRBR) Address: E8h — Write only Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page 2. Bit 1-3. Not used Bit 0. DRBR0. This bit, when set, selects EEP- ROM page 0. The selection of the bank is made by program- ming the Data RAM Bank Switch register (DRBR register) located at address E8h of the Data Space according to Table 1. No more than one bank should be set at a time. The DRBR register can be addressed like a RAM Data Space at the address E8h; nevertheless it is a write only register that cannot be accessed with single-bit operations. This register is used to se- lect the desired 64-byte RAM bank of the Data Space. The number of banks has to be loaded in the DRBR register and the instruction has to point to the selected location as if it was in bank 0 (from 00h address to 3Fh address). This register is not cleared during the MCU initial- ization, therefore it must be written before the first access to the Data Space bank region. Refer to the Data Space description for additional informa- tion. The DRBR register is not modified when an interrupt or a subroutine occurs. Notes : Care is required when handling the DRBR register as it is write only. For this reason, it is not allowed to change the DRBR contents while executing in- terrupt service routine, as the service routine can- not save and then restore its previous content. If it is impossible to avoid the writing of this register in interrupt service routine, an image of this register must be saved in a RAM location, and each time the program writes to DRBR it must write also to the image register. The image register must be written first, so if an interrupt occurs between the two instructions the DRBR is not affected. In DRBR Register, only 1 bit must be set. Other- wise two or more pages are enabled in parallel, producing errors. Table 3. Data RAM Bank Register Set-up 70 -- - DRBR 4 --- DRBR 0 DRBR ST62T52B ST62T62B 00 None None 01 Not available EEPROM page 0 02 Not Available Not Available 08 Not available Not available 10h RAM Page 2 RAM Page 2 other Reserved Reserved 10 |
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