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M48T08 Datasheet(PDF) 10 Page - STMicroelectronics |
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M48T08 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 30 page Operation modes M48T08, M48T08Y, M48T18 10/30 Table 3. Read mode AC characteristics Note: Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). Write mode The M48T08/18/08Y is in the WRITE Mode whenever W, E1, and E2 are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for a minimum of tE1HAX or tE2LAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE Cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE Cycles to avoid bus contention; however, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs tWLQZ after W falls. Symbol Parameter(1) M48T08/M48T18/T08Y Unit –100/–10 (T08Y) –150/–15 (T08Y) Min Max Min Max tAVAV READ Cycle Time 100 150 ns tAVQV Address Valid to Output Valid 100 150 ns tE1LQV Chip Enable 1 Low to Output Valid 100 150 ns tE2HQV Chip Enable 2 High to Output Valid 100 150 ns tGLQV Output Enable Low to Output Valid 50 75 ns tE1LQX Chip Enable 1 Low to Output Transition 10 10 ns tE2HQX Chip Enable 2 High to Output Transition 10 10 ns tGLQX Output Enable Low to Output Transition 5 5 ns tE1HQZ Chip Enable 1 High to Output Hi-Z 50 75 ns tE2LQZ Chip Enable 2 Low to Output Hi-Z 50 75 ns tGHQZ Output Enable High to Output Hi-Z 40 60 ns tAXQX Address Transition to Output Transition 5 5 ns |
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