MDT10C23

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P. 8

2005/6

Ver. 1.2

(B) Program Memory

Address

Description

000- 7FF

Program memory

7FF

The starting address of the power on, external reset or WDT

8. Reset Condition for all Registers

Register

Address

Power-On Reset

/MCLR Reset

WDT Reset

CPIO A

－－

1111 1111

1111 1111

1111 1111

CPIO B

－－

1111 1111

1111 1111

1111 1111

TMR

－－

--11 1111

--11 1111

--11 1111

IAR

00h

－

－

－

RTCC

01h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PC

02h

1111 1111

1111 1111

1111 1111

STATUS

03h

0001 1xxx

000# #uuu

000# #uuu

MSR

04h

100x xxxx

100u uuuu

1uuu uuuu

PORT A

05h

xxxx xxxx

uuuuuuuu

uuuu uuuu

PORT B

06h

xxxx xxxx

uuuu uuuu

uuuu uuuu

CMR

07h

0000 0000

uuuu uuuu

uuuu uuuu

Note : u

＝unchanged, x＝unknown, - ＝unimplemented, read as “0”

#

＝value depends on the condition of the following table

Condition

Status: bit 4

Status: bit 3

/MCLR reset (not during SLEEP)

U

u

/MCLR reset during SLEEP

1

0

WDT reset (not during SLEEP)

0

1

WDT reset during SLEEP

0

0

9. Instruction Set

Instruction Code

Mnemonic

Operands

Function

Operating

Status

010000 00000000

NOP

No operation

None

010000 00000001

CLRWT

Clear Watchdog timer

0

→WT

TF, PF

010000 00000010

SLEEP

Sleep mode

0

→WT, stop OSC

TF, PF