MDT10P55B

This specification are subject to be changed without notice. Any latest information please preview

http;//www.mdtic.com.tw

P. 6

2005/6 Ver. 1.2

(B) Program Memory

Address

Description

000-3FF

Program memory

000

The starting address of power on, external reset or WDT time-out reset.

8. Reset Condition for all Registers

Register

Address

Power-On Reset

/MCLR Reset

WDT Reset

CPIO B

－－

--11 1111

--111 1111

--11 1111

CPIO C

－－

--11 1111

--11 1111

--11 1111

TMR

－－

1111 1111

1111 1111

--11 1111

IAR

00h

xxxx xxxx

uuuu uuuu

uuuu uuuu

RTCC

01h

xxxx xxxx

uuuu uuuu

uuuu uuuu

PC

02h

0000 0000

0000 0000

0000 0000

STATUS

03h

0001 1xxx

#00# #uuu

#00# #uuu

MSR

04h

110x xxxx

11uu uuuu

11uu uuuu

PORT B

06h

--xx xxxx

--uu uuuu

--uu uuuu

PORT C

07h

--xx xxxx

--uu uuuu

--uu uuuu

Note : u

＝unchanged, x＝unknown, - ＝unimplemented, read as “0”

#

＝value depends on the condition of the following table

Condition

Status: bit 7

Status: bit 4

Status: bit 3

/MCLR reset (not during SLEEP)

0

u

u

/MCLR reset during SLEEP

0

1

0

WDT reset (not during SLEEP)

0

0

1

WDT reset during SLEEP

0

0

0

Wake-up from SLEEP on pin change

1

1

0

9. Instruction Set :

Instruction Code

Mnemonic

Operands

Function

Operating

Status

010000 00000000

NOP

No operation

None

010000 00000001

CLRWT

Clear Watchdog timer

0

→WT

TF, PF

010000 00000010

SLEEP

Sleep mode

0

→WT, stop OSC

TF, PF

010000 00000011

TMODE

Load W to TMODE register

W

→TMODE

None

010000 00000100

RET

Return

Stack

→PC

None