List of Tables
Table 1.
Documentation Conventions ............................................................................................ 23
Table 3-1.
Memory Map ................................................................................................................... 48
Table 4-1.
Exception Types .............................................................................................................. 51
Table 4-2.
Interrupts ........................................................................................................................ 52
Table 5-1.
JTAG Port Pins Reset State ............................................................................................. 56
Table 5-2.
JTAG Instruction Register Commands ............................................................................... 61
Table 6-1.
System Control Register Map ........................................................................................... 75
Table 7-1.
Hibernation Module Register Map ................................................................................... 145
Table 8-1.
Flash Protection Policy Combinations ............................................................................. 162
Table 8-2.
Flash Resident Registers ............................................................................................... 163
Table 8-3.
Flash Register Map ........................................................................................................ 164
Table 9-1.
DMA Channel Assignments ............................................................................................ 191
Table 9-2.
Request Type Support ................................................................................................... 192
Table 9-3.
Control Structure Memory Map ....................................................................................... 193
Table 9-4.
Channel Control Structure .............................................................................................. 193
Table 9-5.
μDMA Read Example: 8-Bit Peripheral ............................................................................ 202
Table 9-6.
μDMA Interrupt Assignments .......................................................................................... 203
Table 9-7.
Channel Control Structure Offsets for Channel 30 ............................................................ 204
Table 9-8.
Channel Control Word Configuration for Memory Transfer Example .................................. 204
Table 9-9.
Channel Control Structure Offsets for Channel 7 .............................................................. 205
Table 9-10.
Channel Control Word Configuration for Peripheral Transmit Example .............................. 206
Table 9-11.
Primary and Alternate Channel Control Structure Offsets for Channel 8 ............................. 207
Table 9-12.
Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ............... 208
Table 9-13.
μDMA Register Map ...................................................................................................... 209
Table 10-1.
GPIO Pad Configuration Examples ................................................................................. 255
Table 10-2.
GPIO Interrupt Configuration Example ............................................................................ 256
Table 10-3.
GPIO Register Map ....................................................................................................... 257
Table 11-1.
Available CCP Pins ........................................................................................................ 298
Table 11-2.
16-Bit Timer With Prescaler Configurations ..................................................................... 301
Table 11-3.
Timers Register Map ...................................................................................................... 307
Table 12-1.
Watchdog Timer Register Map ........................................................................................ 332
Table 13-1.
Samples and FIFO Depth of Sequencers ........................................................................ 355
Table 13-2.
Differential Sampling Pairs ............................................................................................. 357
Table 13-3.
ADC Register Map ......................................................................................................... 360
Table 14-1.
UART Register Map ....................................................................................................... 393
Table 15-1.
SSI Register Map .......................................................................................................... 440
Table 16-1.
Examples of I2C Master Timer Period versus Speed Mode ............................................... 471
Table 16-2.
Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 480
Table 16-3.
Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 485
Table 17-1.
Univeral Serial Bus (USB) Controller Register Map .......................................................... 514
Table 18-1.
Comparator 0 Operating Modes ...................................................................................... 592
Table 18-2.
Comparator 1 Operating Modes ..................................................................................... 593
Table 18-3.
Internal Reference Voltage and ACREFCTL Field Values ................................................. 593
Table 18-4.
Analog Comparators Register Map ................................................................................. 595
Table 19-1.
PWM Register Map ........................................................................................................ 610
Table 20-1.
QEI Register Map .......................................................................................................... 660
11
April 08, 2008
Preliminary
LM3S3748 Microcontroller