List of Figures
Figure 1-1.
Stellaris
® 600 Series High-Level Block Diagram ................................................................ 24
Figure 2-1.
CPU Block Diagram ......................................................................................................... 31
Figure 2-2.
TPIU Block Diagram ........................................................................................................ 32
Figure 5-1.
JTAG Module Block Diagram ............................................................................................ 41
Figure 5-2.
Test Access Port State Machine ....................................................................................... 44
Figure 5-3.
IDCODE Register Format ................................................................................................. 48
Figure 5-4.
BYPASS Register Format ................................................................................................ 48
Figure 5-5.
Boundary Scan Register Format ....................................................................................... 49
Figure 6-1.
External Circuitry to Extend Reset .................................................................................... 51
Figure 6-2.
Main Clock Tree .............................................................................................................. 54
Figure 7-1.
Flash Block Diagram ...................................................................................................... 108
Figure 8-1.
GPIO Port Block Diagram ............................................................................................... 125
Figure 8-2.
GPIODATA Write Example ............................................................................................. 126
Figure 8-3.
GPIODATA Read Example ............................................................................................. 126
Figure 9-1.
GPTM Module Block Diagram ........................................................................................ 163
Figure 9-2.
16-Bit Input Edge Count Mode Example .......................................................................... 167
Figure 9-3.
16-Bit Input Edge Time Mode Example ........................................................................... 168
Figure 9-4.
16-Bit PWM Mode Example ............................................................................................ 169
Figure 10-1.
WDT Module Block Diagram .......................................................................................... 198
Figure 11-1.
ADC Module Block Diagram ........................................................................................... 222
Figure 11-2.
Internal Temperature Sensor Characteristic ..................................................................... 225
Figure 12-1.
UART Module Block Diagram ......................................................................................... 255
Figure 12-2.
UART Character Frame ................................................................................................. 256
Figure 13-1.
SSI Module Block Diagram ............................................................................................. 292
Figure 13-2.
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 294
Figure 13-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 295
Figure 13-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 296
Figure 13-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 296
Figure 13-6.
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 297
Figure 13-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 298
Figure 13-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 298
Figure 13-9.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 299
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 300
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 301
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 301
Figure 14-1.
I2C Block Diagram ......................................................................................................... 329
Figure 14-2.
I2C Bus Configuration .................................................................................................... 330
Figure 14-3.
START and STOP Conditions ......................................................................................... 330
Figure 14-4.
Complete Data Transfer with a 7-Bit Address ................................................................... 331
Figure 14-5.
R/S Bit in First Byte ........................................................................................................ 331
Figure 14-6.
Data Validity During Bit Transfer on the I2C Bus ............................................................... 331
Figure 14-7.
Master Single SEND ...................................................................................................... 334
Figure 14-8.
Master Single RECEIVE ................................................................................................. 335
Figure 14-9.
Master Burst SEND ....................................................................................................... 336
Figure 14-10. Master Burst RECEIVE .................................................................................................. 337
October 01, 2007
8
Preliminary
Table of Contents