6.1.3
Non-Maskable Interrupt ............................................................................................................. 69
6.1.4
Power Control ........................................................................................................................... 69
6.1.5
Clock Control ............................................................................................................................ 69
6.1.6
System Control ......................................................................................................................... 73
6.2
Initialization and Configuration ................................................................................................... 74
6.3
Register Map ............................................................................................................................ 75
6.4
Register Descriptions ................................................................................................................ 76
7
Hibernation Module .......................................................................................................... 137
7.1
Block Diagram ........................................................................................................................ 138
7.2
Functional Description ............................................................................................................. 138
7.2.1
Register Access Timing ........................................................................................................... 138
7.2.2
Clock Source .......................................................................................................................... 139
7.2.3
Battery Management ............................................................................................................... 141
7.2.4
Real-Time Clock ...................................................................................................................... 142
7.2.5
Non-Volatile Memory ............................................................................................................... 142
7.2.6
Power Control ......................................................................................................................... 142
7.2.7
Interrupts and Status ............................................................................................................... 143
7.3
Initialization and Configuration ................................................................................................. 143
7.3.1
Initialization ............................................................................................................................. 143
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 144
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 144
7.3.4
External Wake-Up from Hibernation .......................................................................................... 144
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 144
7.3.6
Register Reset ........................................................................................................................ 144
7.4
Register Map .......................................................................................................................... 145
7.5
Register Descriptions .............................................................................................................. 146
8
Internal Memory ............................................................................................................... 160
8.1
Block Diagram ........................................................................................................................ 160
8.2
Functional Description ............................................................................................................. 160
8.2.1
SRAM Memory ........................................................................................................................ 160
8.2.2
ROM Memory ......................................................................................................................... 161
8.2.3
Flash Memory ......................................................................................................................... 161
8.3
Flash Memory Initialization and Configuration ........................................................................... 162
8.3.1
Flash Programming ................................................................................................................. 162
8.3.2
Nonvolatile Register Programming ........................................................................................... 163
8.4
Register Map .......................................................................................................................... 164
8.5
ROM Register Descriptions (System Control Offset) .................................................................. 165
8.6
Flash Register Descriptions (Flash Control Offset) ..................................................................... 166
8.7
Flash Register Descriptions (System Control Offset) .................................................................. 173
9
Micro Direct Memory Access (μDMA) ............................................................................ 189
9.1
Block Diagram ........................................................................................................................ 190
9.2
Functional Description ............................................................................................................. 190
9.2.1
Channel Assigments ................................................................................................................ 191
9.2.2
Priority .................................................................................................................................... 191
9.2.3
Arbitration Size ........................................................................................................................ 191
9.2.4
Request Types ........................................................................................................................ 192
9.2.5
Channel Configuration ............................................................................................................. 192
9.2.6
Transfer Modes ....................................................................................................................... 194
April 08, 2008
4
Preliminary
Table of Contents