List of Figures
Figure 1-1.
Stellaris® Fury-class Family High-Level Block Diagram ...................................................... 22
Figure 2-1.
CPU Block Diagram ......................................................................................................... 29
Figure 2-2.
TPIU Block Diagram ........................................................................................................ 30
Figure 5-1.
JTAG Module Block Diagram ............................................................................................ 39
Figure 5-2.
Test Access Port State Machine ....................................................................................... 42
Figure 5-3.
IDCODE Register Format ................................................................................................. 47
Figure 5-4.
BYPASS Register Format ................................................................................................ 48
Figure 5-5.
Boundary Scan Register Format ....................................................................................... 48
Figure 6-1.
External Circuitry to Extend Reset .................................................................................... 50
Figure 7-1.
Hibernation Module Block Diagram ................................................................................. 103
Figure 8-1.
Flash Block Diagram ...................................................................................................... 121
Figure 9-1.
GPIODATA Write Example ............................................................................................. 146
Figure 9-2.
GPIODATA Read Example ............................................................................................. 146
Figure 10-1.
GPTM Module Block Diagram ........................................................................................ 186
Figure 10-2.
16-Bit Input Edge Count Mode Example .......................................................................... 190
Figure 10-3.
16-Bit Input Edge Time Mode Example ........................................................................... 191
Figure 10-4.
16-Bit PWM Mode Example ............................................................................................ 192
Figure 11-1.
WDT Module Block Diagram .......................................................................................... 221
Figure 12-1.
UART Module Block Diagram ......................................................................................... 245
Figure 12-2.
UART Character Frame ................................................................................................. 246
Figure 12-3.
IrDA Data Modulation ..................................................................................................... 248
Figure 13-1.
SSI Module Block Diagram ............................................................................................. 285
Figure 13-2.
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 288
Figure 13-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 288
Figure 13-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 289
Figure 13-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 289
Figure 13-6.
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 290
Figure 13-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 291
Figure 13-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 291
Figure 13-9.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 292
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 293
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 294
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 294
Figure 14-1.
Analog Comparator Module Block Diagram ..................................................................... 322
Figure 14-2.
Structure of Comparator Unit .......................................................................................... 323
Figure 14-3.
Comparator Internal Reference Structure ........................................................................ 324
Figure 15-1.
Pin Connection Diagram ................................................................................................ 334
Figure 18-1.
Load Conditions ............................................................................................................ 350
Figure 18-2.
Hibernation Module Timing ............................................................................................. 352
Figure 18-3.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 352
Figure 18-4.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 353
Figure 18-5.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 353
Figure 18-6.
JTAG Test Clock Input Timing ......................................................................................... 354
Figure 18-7.
JTAG Test Access Port (TAP) Timing .............................................................................. 355
Figure 18-8.
JTAG TRST Timing ........................................................................................................ 355
Figure 18-9.
External Reset Timing (RST) .......................................................................................... 356
7
September 02, 2007
Preliminary
LM3S1110 Microcontroller