Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 375
Figure 15-12. Master Burst SEND after Burst RECEIVE ........................................................................ 376
Figure 15-13. Slave Command Sequence ............................................................................................ 377
Figure 16-1.
Ethernet Controller Block Diagram .................................................................................. 402
Figure 16-2.
Ethernet Controller ......................................................................................................... 402
Figure 16-3.
Ethernet Frame ............................................................................................................. 404
Figure 17-1.
PWM Module Block Diagram .......................................................................................... 445
Figure 17-2.
PWM Count-Down Mode ................................................................................................ 446
Figure 17-3.
PWM Count-Up/Down Mode .......................................................................................... 447
Figure 17-4.
PWM Generation Example In Count-Up/Down Mode ....................................................... 447
Figure 17-5.
PWM Dead-Band Generator ........................................................................................... 448
Figure 18-1.
Pin Connection Diagram ................................................................................................ 480
Figure 21-1.
Load Conditions ............................................................................................................ 498
Figure 21-2.
I2C Timing ..................................................................................................................... 500
Figure 21-3.
External XTLP Oscillator Characteristics ......................................................................... 503
Figure 21-4.
Hibernation Module Timing ............................................................................................. 504
Figure 21-5.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 504
Figure 21-6.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 505
Figure 21-7.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 505
Figure 21-8.
JTAG Test Clock Input Timing ......................................................................................... 506
Figure 21-9.
JTAG Test Access Port (TAP) Timing .............................................................................. 507
Figure 21-10. JTAG TRST Timing ........................................................................................................ 507
Figure 21-11. External Reset Timing (RST) .......................................................................................... 508
Figure 21-12. Power-On Reset Timing ................................................................................................. 508
Figure 21-13. Brown-Out Reset Timing ................................................................................................ 508
Figure 21-14. Software Reset Timing ................................................................................................... 509
Figure 21-15. Watchdog Reset Timing ................................................................................................. 509
Figure 22-1.
100-Pin LQFP Package .................................................................................................. 510
9
November 30, 2007
Preliminary
LM3S6916 Microcontroller