SN55LBC175

QUADRUPLE LOW-POWER DIFFERENTIAL LINE RECEIVER

SGLS083A – MARCH 1995 – REVISED JUNE 2000

2

POST OFFICE BOX 655303

2B

2A

1B

1A

1, 2EN

2Y

1Y

5

3

7

6

1

2

4

EN

4B

4A

3B

3A

3, 4EN

4Y

3Y

13

11

15

14

9

10

12

EN

Pin numbers shown are for the J or W package.

† This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

logic diagram (positive logic)

2Y

1Y

5

3

7

6

1

2

4

2B

2A

1B

1A

1, 2EN

4Y

3Y

13

11

15

14

9

10

12

4B

4A

3B

3A

3, 4EN

schematics of inputs and outputs

TYPICAL OF ALL OUTPUTS

VCC

Y Output

EQUIVALENT OF A AND B INPUTS

12 k

Ω

3 k

Ω

18 k

Ω

1 k

Ω

VCC

Input

100 k

Ω

A Only

100 k

Ω

B Only

Input

VCC

TYPICAL OF EN INPUT