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UCC37322DG4 Datasheet(PDF) 1 Page - Texas Instruments |
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UCC37322DG4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 28 page UCC27321, UCC27322 UCC37321, UCC37322 SLUS504D − SEPTEMBER 2002 − REVISED SEPTEMBER 2007 SINGLE 9A HIGH SPEED LOW-SIDE MOSFET DRIVER WITH ENABLE 1 www.ti.com FEATURES D Industry-Standard Pin-Out With Addition of Enable Funtion D High-Peak Current Drive Capability of ±9 A at the Miller Plateau Region Using TrueDrive D Efficient Constant Current Sourcing Using a Unique BiPolar & CMOS Output Stage D TTL/CMOS Compatible Inputs Independent of Supply Voltage D 20-ns Typical Rise and Fall Times with 10-nF Load D Typical Propagation Delay Times of 25 ns With Input Falling and 35 ns with Input Rising D 4-V to 15-V Supply Voltage D Available in Thermally Enhanced MSOP PowerPADTM Package With 4.7 °C/W θjc D Rated From –40°C to 105°C D Pb-Free Finish (NiPdAu) on SOIC-8 and PDIP-8 Packages APPLICATIONS D Switch Mode Power Supplies D DC/DC Converters D Motor Controllers D Class-D Switching Amplifiers D Line Drivers D Pulse Transformer Driver DESCRIPTION The UCC37321/2 family of high-speed drivers deliver 9 A of peak drive current in an industry standard pinout. These drivers can drive the largest of MOSFETs for systems requiring extreme Miller current due to high dV/dt transitions. This eliminates additional external circuits and can replace multiple components to reduce space, design complexity and assembly cost. Two standard logic options are offered, inverting (UCC37321) and noninverting (UCC37322). PowerPAD t is trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UDG−01112 1 OUT VDD IN 3 ENBL 7 VDD 8 INVERTING NON− INVERTING PGND 6 OUT 5 4 AGND VDD 2 INVERTING UCC37321 0 0 0 0 1 0 0 1 1 1 1 0 NON− INVERTING UCC37322 0 0 0 0 1 0 0 0 1 1 1 1 ENBL IN OUT INPUT/OUTPUT TABLE RENBL 100 k Ω |
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