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UCC27322PE4 Datasheet(PDF) 7 Page - Texas Instruments |
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UCC27322PE4 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 28 page UCC27321, UCC27322 UCC37321, UCC37322 SLUS504D − SEPTEMBER 2002 − REVISED SEPTEMBER 2007 7 www.ti.com APPLICATION INFORMATION output stage The TrueDrive output stage is capable of supplying ±9-A peak current pulses and swings to both VDD and GND and can encourage even the most stubborn MOSFETs to switch. The pull-up/pull-down circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the internal MOSFET. This means that in many cases, external-schottky-clamp diodes are not required. This unique BiPolar and MOSFET hybrid output architecture (TrueDrive) allows efficient current sourcing at low supply voltages. The UCC37321/2 family delivers 9 A of gate drive where it is most needed during the MOSFET switching transition – at the Miller plateau region – providing improved efficiency gains. source/sink capabilities during miller plateau Large power MOSFETs present a significant load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC37321/2 drivers have been optimized to provide maximum drive to a power MOSFET during the Miller Plateau Region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with current supplied or removed by the driver device. [1] Two circuits are used to test the current capabilities of the UCC37321/2 driver. In each case external circuitry is added to clamp the output near 5 V while the device is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where the current peaked up and then settled down to a steady-state value. The noted current measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient. The circuit in Figure 3 is used to verify the current sink capability when the output of the driver is clamped around 5 V, a typical value of gate-source voltage during the Miller Plateau Region. The UCC37321 is found to sink 9 A at VDD = 15 V. UDG−01113 UCC37321 ENBL 1 2 3 4 AGND IN 7 6 5 8 OUT OUT PGND INPUT 1 µF CER 100 µF AL EL DSCHOTTKY VDD C2 1 µF VSNS RSNS 0.1 Ω C3 100 µF 10 Ω + VSUPPLY 5.5 V VDD VDD Figure 3. Sink Current Test Circuit |
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