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V4374128C24V Datasheet(PDF) 6 Page - Mosel Vitelic, Corp |
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V4374128C24V Datasheet(HTML) 6 Page - Mosel Vitelic, Corp |
6 / 13 page 6 V4374128C24V Rev. 1.1 January 2002 MOSEL VITELIC V4374128C24V 28 Minimum Row Active to Row Active Delay tRRD 14 ns/15 ns/16 ns 0F 0F 0F 29 Minimum RAS to CAS Delay tRCD 15 ns/20 ns 0F 14 14 30 Minimum RAS Pulse Width tRAS 42 ns/45 ns 2A 2D 2D 31 Module Bank Density (Per Bank) 512 MByte 80 80 80 32 SDRAM Input Setup Time 1.5 ns/2.0 ns 15 15 20 33 SDRAM Input Hold Time 0.8 ns/1.0 ns 08 08 10 34 SDRAM Data Input Setup Time 1.5 ns/2.0 ns 15 15 20 35 SDRAM Data Input Hold Time 0.8 ns/1.0 ns 08 08 10 36-61 Superset Information (May be used in Fu- ture) 00 00 00 62 SPD Revision Revision 2/1.2 02 02 12 63 Checksum for Bytes 0 - 62 69 AD 1A 64 Manufacturer’s JEDEC ID Code Mosel Vitelic 40 40 40 65-71 Manufacturer’s JEDEC ID Code (cont.) 00 00 00 72 Manufacturing Location 73-90 Module Part Number (ASCII) V4374128C24V 91-92 PCB Identification Code 93 Assembly Manufacturing Date (Year) 94 Assembly Manufacturing Date (Week) 95-98 Assembly Serial Number 99-125 Reserved 00 00 00 126 Intel Specification for Frequency 64 64 64 127 Reserved 8D 8D 8D 128+ Unused Storage Location 00 00 00 SPD-Table: (Continued) Byte Num- ber Function Described SPD Entry Value Hex Value -75PC -75 -10PC |
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