1

PS8609A

01/13/05

Features

• Maximumratedfrequency:133MHz

• Low cycle-to-cycle jitter

• Input to output delay, less than 200ps

• External feedback pin allows outputs to be synchronized

to the clock input

• 5V tolerant input*

• Operates at 3.3V V

DD

• Test mode allows bypass of the PLL for system testing

purposes (e.g., IBIS measurements)

• Space-saving Packaging (Pb-free and Green Available):

— 8-pin, 150-mil SOIC (W)

Description

The PI6C2404A-1 is a PLL-based, zero-delay buffer, with the ability

to distribute four outputs of up to 133 MHz at 3.3V. Two banks of

two outputs exist, OUTA[1–2] and OUTB[1–2].

An external feedback pin is used to synchronize the outputs to the

input; the relationship between loading of this signal and the other

outputs determines the input-output delay.

The PI6C2404A-1 is characterized for both commercial and industrial

operation.

Block Diagram

PinConfiguration

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Zero-Delay Clock Buffer

PI6C2404A-1

* FB_IN and CLKIN must reference the same voltage thresh-

olds for the PLL to deliver zero delay skewing

1

2

3

GND

4

OUTA2

FB_IN

OUTB2

OUTB1

8

7

6

5

CLKIN

OUTA1

VDD

8-Pin

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Pin Description

PLL

CLKIN

FB_IN

OUTA1

OUTA2

OUTB2

OUTB1

06-0036