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LTC3560ES6PBF Datasheet(PDF) 11 Page - Linear Technology |
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LTC3560ES6PBF Datasheet(HTML) 11 Page - Linear Technology |
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11 / 16 page  11 LTC3560 3560f APPLICATIO S I FOR ATIO both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3560 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The tempera- ture rise is given by: TR = (PD)(θJA) where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3560 in dropout at an input voltage of 2.7V, a load current of 800mA and an ambient temperature of 70 °C. From the typical perfor- mance graph of switch resistance, the RDS(ON) of the P-channel switch at 70 °C is approximately 0.31Ω. There- fore, power dissipated by the part is: PD = ILOAD2 • RDS(ON) = 198mW For the SOT-23 package, the θJA is 250°C/W. Thus, the junction temperature of the regulator is: TJ = 70°C + (0.198)(250) = 120°C which is below the maximum junction temperature of 125 °C. Note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ( ∆ILOAD • ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or dis- charge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady-state value. During this recovery time VOUTcan be monitored for overshoot or ringing that would indicate a stability prob- lem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1 µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10 µF capacitor charging to 3.3V would require a 250 µs rise time, limiting the charging current to about 130mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3560. These items are also illustrated graphically in Figures 4 and 5. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1/R2 must be con- nected between the (+) plate of COUT and ground. 3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 4. Keep the (–) plates of CIN and COUT as close as possible. 5. Keep the switching node, SW, away from the sensitive VFB node. Design Example As a design example, assume the LTC3560 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 0.8A but most of the time it will be in |
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