CDCE72010RGCT datasheet(58/70 Pages) TI

Part #	CDCE72010RGCT

Description	Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor

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Manufacturer	TI [Texas Instruments]

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EXTERNAL/HOLD FUNCTION

INTERNAL/HOLD FUNCTION

3-State

ChargePump

yes

no

PLL

Out-of-Lock

PLL-Lock

OutputSet

no

64PFD

LockCycles

Ref.Clock

isBack

no

Start

PLL isout- of-lockifthephase

differenceof ReferenceClock and

FeedbackClock

atPFDareoutsidethe

predefinedLock-Detect-Windoworifa

Cycle- Slipoccurs.

FrequencyHold-OverFunctionworksin

combinationwiththe AnalogLock -Detect

Charge- Pumpisswitchedinto 3-State.

PLL hastobeinLOCKtostart

HOLD-Function.

( The AnalogLockoutputisnotresetbythefirstOut-of-

Lockevent. Itstays ‘High’ dependingontheanalogtime

delay ( outputC-load). Thetimedelaymustbelongenough

toguaranteeproperHOLDfunction)

TheCharge-Pumpremainsinto 3-State

untilthe ReferenceClock isback. The 1

st

valid ReferenceClock atthePFDreleases

theCharge- Pump.

ThePLL acquire 64 lockcyclestophase

aligntotheinputclock.

CDCE72010

SCAS858 – JUNE 2008...................................................................................................................................................................................................... www.ti.com

The Charge Pump can directly be switched into 3-State. This function is also available via SPI register. If logic

low is applied to HOLD pin the Charge Pump will be switched to 3-State. After HOLD pin is released, the charge

pump is switched back in to normal operation, with the next valid reference clock cycle at PRI_REF or SEC_REF

and the next valid feedback clock cycle at the PFD. During HOLD, all divider and all outputs are at normal

operation.

In Internal HOLD Function or HOLD-Over-Function the PLL has to be in lock to start the HOLD function. It

switches the Charge Pump in to 3-State when an ‘out-of-lock’ event occurs. It leaves the ‘3-State Charge Pump’

state when the Reference Clock is back. Then it starts a locking sequence of 64 cycles before it goes back to the

beginning of the HOLD-Over loop.

Figure 24. Frequency Hold Over

58

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