EM681FV16AU Series
Low Power, 512Kx16 SRAM
5
Parameter
Symbol
45ns
55ns
70ns
Unit
Min
Max
Min
Max
Min
Max
Read cycle time
tRC
45
-
55
-
70
-
ns
Address access time
tAA
-45
-
55
-70
ns
Chip select to output
tco
-45
-
55
-70
ns
Output enable to valid output
tOE
-30
-
35
-35
ns
UB, LB access time
tBA
45
55
70
ns
Chip select to low-Z output
tLZ
5-5-5-
ns
UB, LB enable to low-Z output
tBLZ
5-5-5-
ns
Output enable to low-Z output
tOLZ
5-5-5-
ns
Chip disable to high-Z output
tHZ
020
0
20
025
ns
UB, LB disable to how-Z output
tBHZ
020
0
20
025
ns
Output disable to high-Z output
tOHZ
020
0
20
025
ns
Output hold from address change
tOH
10
-
10
-
10
-
ns
Parameter
Symbol
45ns
55ns
70ns
Unit
Min
Max
Min
Max
Min
Max
Write cycle time
tWC
45
-
55
-
70
-
ns
Chip select to end of write
tCW
45
-
45
-
60
-
ns
Address setup time
tAs
0-
0-
0-
ns
Address valid to end of write
tAW
45
-
45
-
60
-
ns
UB, LB valid to end of write
tBW
45
-
45
-
60
-
ns
Write pulse width
tWP
45
-
45
-
55
-
ns
Write recovery time
tWR
0-
0-
0-
ns
Write to ouput high-Z
tWHZ
020
0
20
025
ns
Data to write time overlap
tDW
25
30
30
ns
Data hold from write time
tDH
0-
0-
0-
ns
End write to output low-Z
tOW
5-
5
5
-
ns
READ CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40
oC to +85oC)
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40
oC to +85oC)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
Input Pulse Level : 0.4 to 2.4V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL1) = 100pF + 1 TTL (70nsec)
CL1) = 30pF + 1 TTL (45ns/55ns)
1. Including scope and Jig capacitance
2. R1=3070 ohm,
R2=3150 ohm
3. VTM=2.8V
4. CL = 5pF + 1 TTL (measurement with tLZ, tHZ, tOLZ, tOHZ, tWHZ)
CL1)
VTM
3)
R1
2)
R2
2)
