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SN54ABT16833 Datasheet(PDF) 8 Page - Texas Instruments |
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SN54ABT16833 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 13 page SN54ABT16833, SN74ABT16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS097D – FEBRUARY 1991 – REVISED JANUARY 1997 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C SN54ABT16833 SN74ABT16833 UNIT MIN MAX MIN MAX MIN MAX tw Pulse duration, CLK high or low 3 3 3 ns ↑ A port 4.5 4.5 4.5 tsu Setup time before CLK ↑ CLR 1 1 1 ns OEA 5 5 5 th Hold time after CLK ↑ A port or OEA 0 0 0 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C SN54ABT16833 SN74ABT16833 UNIT (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX tPLH AorB BorA 1.5 2.5 3.3 1.5 4.2 1.5 4.1 ns tPHL A or B B or A 2 3.1 3.9 2 4.5 2 4.3 ns tPZH OE AorB 2 3.9 4.9 2 5.8 2 5.6 ns tPZL OE A or B 2.5 4.3 5.1 2.5 6.2 2.5 6 ns tPHZ OE AorB 2 3.6 4.5 2 5.5 2 5.4 ns tPLZ OE A or B 1.5 3 3.8 1.5 4.7 1.5 4.3 ns tPLH AorOE PARITY 2 4.6 5.4 2 7 2 6.7 ns tPHL A or OE PARITY 2 4.3 5.1 2 6.5 2 6.1 ns tPZH OE PARITY 2 3.6 5 2 5.8 2 5.7 ns tPZL OE PARITY 2.5 4.4 5.8 2.5 6.7 2.5 6.5 ns tPHZ OE PARITY 1.5 3.2 4 1.5 4.8 1.5 4.7 ns tPLZ OE PARITY 1.5 2.9 3.7 1.5 4.2 1.5 4.1 ns tPLH CLK, CLR ERR 2 3.4 4.2 2 4.8 2 4.6 ns tPHL CLK ERR 2 2.8 3.6 2 4.1 2 3.9 ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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