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PSD9342V20MIT Datasheet(PDF) 9 Page - STMicroelectronics |
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PSD9342V20MIT Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 89 page 9/89 PSD834F2V In-System Programming (ISP) Using the JTAG signals on Port C, the entire PSD device can be programmed or erased without the use of the MCU. The primary Flash memory can also be programmed in-system by the MCU exe- cuting the programming algorithms out of the sec- ondary memory, or SRAM. The secondary memory can be programmed the same way by ex- ecuting out of the primary Flash memory. The PLD or other PSD Configuration blocks can be pro- grammed through the JTAG port or a device pro- grammer. Table 3 indicates which programming methods can program different functional blocks of the PSD. Table 3. Methods of Programming Different Functional Blocks of the PSD Power Management Unit (PMU) The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit has a Power-down mode that helps reduce power consumption. The PSD also has some bits that are configured at run-time by the MCU to reduce power consump- tion of the CPLD. The Turbo bit in PMMR0 can be reset to 0 and the CPLD latches its outputs and goes to sleep until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. Please see the sec- tion entitled “Power Management” on page 55 for more details. Functional Block JTAG Programming Device Programmer IAP Primary Flash Memory Yes Yes Yes Secondary Flash Memory Yes Yes Yes PLD Array (DPLD and CPLD) Yes Yes No PSD Configuration Yes Yes No |
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