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TPS62293DRVTG4 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS62293DRVTG4 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 24 page www.ti.com PIN ASSIGNMENTS DRV PACKAGE (TOPVIEW) MODE FB GND SW EN VIN 1 2 3 6 5 4 r Po w e P A D FUNCTIONAL BLOCK DIAGRAM Zero-Pole AMP. Integrator Error Amp PFMComp . +1% Voltagepositioning PWM Comp . VREF Control Stage GateDriver Anti Shoot-Through Current LimitComparator Current LimitComparator VREF+1% FB FB VIN GND MODE SW 1 EN VIN Softstart VOUT RAMP CONTROL Thermal Shutdown Reference 0.6VVREF Undervoltage Lockout1.8V Limit HighSide Limit LowSide Sawtooth Generator Int. Resistor Network FB RI1 RI..N Mode GND 2.25MHz Oscillator TPS62290, TPS62291, TPS62293 SLVS764C – JUNE 2007 – REVISED MARCH 2008 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. VIN 5 PWR VIN power supply pin. GND 6 PWR GND supply pin This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling EN 4 I this pin to high enables the device. This pin must be terminated. This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor SW 1 OUT between this terminal and the output capacitor. Feedback Pin for the internal regulation loop. Connect the external resistor divider to this pin. In case of FB 3 I fixed output voltage option, connect this pin directly to the output capacitor MODE pin = high forces the device to operate in fixed-frequency PWM mode. Mode pin = low enables MODE 2 I the Power Save Mode with automatic transition from PFM mode to fixed-frequency PWM mode. 4 Submit Documentation Feedback Copyright © 2007–2008, Texas Instruments Incorporated Product Folder Link(s): TPS62290 TPS62291 TPS62293 |
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