KM416S1120DT-GF8 datasheet(9/43 Pages) SAMSUNG

Part #	KM416S1120DT-GF8

Description	512K x 16bit x 2 Banks Synchronous DRAM LVTTL

Download	43 Pages

Scroll/Zoom	100%

Manufacturer	SAMSUNG [Samsung semiconductor]

Direct Link	http://www.samsung.com/Products/Semiconductor

Logo

9 / 43 page

KM416S1120D

CMOS SDRAM

- 9 -

Rev. 1.4 (Jun. 1999)

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

′t Care, H=Logic High, L=Logic Low)

COMMAND

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM

BA

A10/AP

A9~ A0

Note

Register

Mode Register Set

H

X

L

X

OP CODE

1, 2

Refresh

Auto Refresh

H

L

H

X

3

Self

Refresh

Entry

L

3

Exit

L

H

L

H

X

3

H

X

3

Bank Active & Row Addr.

H

X

L

H

X

V

Row Address

Read &

Column Address

Auto Precharge Disable

H

X

L

H

L

H

X

V

L

Column

Address

(A0~A7)

4

Auto Precharge Enable

H

4, 5

Write &

Column Address

Auto Precharge Disable

H

X

L

H

L

X

V

L

Column

Address

(A0~A7)

4

Auto Precharge Enable

H

4, 5

Burst Stop

H

X

L

H

L

X

6

Precharge

Bank Selection

H

X

L

H

L

X

V

L

X

Both Banks

X

H

Clock Suspend or

Active Power Down

Entry

H

L

H

X

L

V

Exit

L

H

X

Precharge Power Down Mode

Entry

H

L

H

X

L

H

Exit

L

H

X

L

V

DQM

H

V

X

7

No Operation Command

H

X

H

X

L

H

1. OP Code : Operand Code

A0 ~ A10/AP, BA : Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.

A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at both banks precharge state.

4. BA : Bank select address.

If "Low" at read, write, row active and precharge, bank A is selected.

If "High" at read, write, row active and precharge, bank B is selected.

If A10/AP is "High" at row precharge, BA is ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the assoiated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Note :

X

Similar Part No. - KM416S1120DT-GF8

Manufacturer	Part #	Datasheet	Description
List of Unclassifed Man...	KM416S1120DT-G/F10	1Mb / 43P	512K x 16bit x 2 Banks Synchronous DRAM LVTTL
	KM416S1120DT-G/F6	1Mb / 43P	512K x 16bit x 2 Banks Synchronous DRAM LVTTL
	KM416S1120DT-G/F7	1Mb / 43P	512K x 16bit x 2 Banks Synchronous DRAM LVTTL
	KM416S1120DT-G/F8	1Mb / 43P	512K x 16bit x 2 Banks Synchronous DRAM LVTTL
	KM416S1120DT-G/FC	1Mb / 43P	512K x 16bit x 2 Banks Synchronous DRAM LVTTL

More results

Similar Description - KM416S1120DT-GF8

Manufacturer	Part #	Datasheet	Description
List of Unclassifed Man...	KM416S1120D	1Mb / 43P	512K x 16bit x 2 Banks Synchronous DRAM LVTTL
Samsung semiconductor	K4S161622D	1Mb / 41P	512K x 16Bit x 2 Banks Synchronous DRAM
	KM416S1021C	78Kb / 8P	512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface
	K4S281632B	108Kb / 10P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S281632M	87Kb / 10P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	KM416S8030B	133Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S561632A	127Kb / 10P	256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL
	K4S281632C	47Kb / 9P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S281632D	112Kb / 11P	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
	K4S561632D-TC75000	64Kb / 11P	256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

More results

KM416S1120DT-GF8 Datasheet(PDF) 9 Page - Samsung semiconductor

KM416S1120DT-GF8 Datasheet(HTML) 9 Page - Samsung semiconductor

Similar Part No. - KM416S1120DT-GF8

Similar Description - KM416S1120DT-GF8

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL