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ZPSD211R-B-70J Datasheet(PDF) 11 Page - STMicroelectronics |
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ZPSD211R-B-70J Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 51 page Table 1. PSD211R Pin Descriptions (cont.) PSD211R Family 8 Name Type Description These pins make up Port C. These port pins are configurable, and can have the following functions (see Figure 7): 1. PAD input—when configured as an input, a bit individually PC0 becomes an address or a logic input, depending on your PSDsoft PC1 I/O design file. When declared as an address, the bits are latched PC2 with ALE/AS. 2. PAD output—when configured as an output (i.e. there is an equation written for it in your PSDsoft design file), there is one product term available to it. AD0 AD1 AD2 These pins are the multiplexed, low-order address/data byte AD3 I/O (AD0-AD7). As inputs, address information is latched by the ALE/AS AD4 signal and used internally by the PSD. The pins also serve as MCU AD5 data bus inputs or outputs, depending on the MCU control signals AD6 (RD, WR, etc.). AD7 A8 A9 A10 A11 I/O These pins are the high-order address inputs (A8-A15). A12 A13 A14 A15 GND P Ground Pin VCC P Supply voltage input. Legend: The Type column abbreviations are: I = input only; I/O = input/output; P = power. |
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