Document No. 008-0278-0

Page 3 - 5

Rev. C

MXO45LV/MXO45HSLV

Metal DIP Clock Oscillator

MECHANICAL SPECIFICATIONS

PACKAGE DRAWING

MARKING INFORMATION

NOTES

CMOS/TTL OUTPUT WAVEFORM

TEST CIRCUIT, CMOS LOAD

ENABLE TRUTH TABLE

PIN 1

PIN 5 or PIN 8

Logic ‘1’

Output

Open

Output

Logic ‘0’

High Imp.

D.U.T. PIN ASSIGNMENTS

PIN

SYMBOL

DESCRIPTION

1

EOH

Enable Input

7 or 4

GND

Circuit & Package Ground

8 or 5

Output

RF Output

14 or 8

Supply Voltage

1. XXXMXXXX - Frequency marked with 4 significant digits after the ‘M’.

2. ST – Frequency stability/temperature code.

(Reference Ordering Information.)

3. YYWW – Date code, YY – year, WW – week.

4. ** - Manufacturing Site Code.

1. Lead finish (e1), SnAgCu.

2. Reflow conditions per JEDEC J-STD-020.

PERIOD (T)

90%, 80%, 2.4V

50%, 1.5V

10%, 20%, 0.5V

DUTY CYCLE = t/T x 100 (%)

V

V

OH

OL

Tr

Tf

UPTIME (t)

POWER

SUPPLY

+

-

+-

-

+

VM

mA

0.01uF

D.U.T.

14 or 8

8 or 5

17 or 4

capacitance.

Enable Input or N.C.

DIP-14

1.524

20.574

.810

.017/.020

.432/.508

6.350 ± .508

5.080

.200

MAX

.250 ± .020

.028 ± .013

INCH

KEY:

MM

.060

.711 ± .330

MAX

.300 ± .005

7.620 ± .127

.510

12.954

FOR REFERENCE

ONLY. THE NUMBERS

ARE NOT MARKED

8

14

1.524

15.240 ± .127

.060

.600 ± .005

TYP.

TYP.

DENOTES PIN 1

1

ON BOTTOM.

7

MAX

MXO45LV

XXXMXXXX

CTS

ST

● YYWW **