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STA015 Datasheet(PDF) 11 Page - STMicroelectronics |
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STA015 Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 55 page  11/55 STA015 STA015B STA015T proper operation BIT_EN line should be toggled only when SCKR is stable low (for both SCLK_POL con- figuration). The possible configurations are described in Fig. 8. 3.2 GPSO Output Interface In order to retrieve ADPCM encoded data a General Purpose Serial Output interface is available (in TQFP44 and LFBGA64 packages only). The maximum frequency for GPSO_SCKR clock is the DSP sys- tem clock frequency divided by 3 (i.e. 8.192 MHz @ 24.58MHz). The interface is based on a simple and configurable 3-lines protocol, as described by figure 10. 3.3 PCM Output Interface The decoded audio data are output in serial PCM format. The interface consists of the following signals: SDO PCM Serial Data Output SCKT PCM Serial Clock Output LRCLK Left/Right Channel Selection Clock The output samples precision is selectable from 16 to 24 bits/word, by setting the output precision with PCMCONF (16, 18, 20 and 24 bits mode) register. Data can be output either with the most significant bit first (MS) or least significant bit first LS), selected by writing into a flag of the PCMCONF register. Figure 9 gives a description of the several STA015 PCM Output Formats. The sample rates set decoded by STA015 is described in Table 1. To enable the GPSO interface bit GEN of GPSO_ENABLE register must be set. Using the GPSO_CONF register the protocol can be configured in order to provide outcoming data on rising/ falling edge of GPSO_SCKR input clock; the GPSO_REQ request signal polarity (usually connected to an MCU interrupt line) can be configured as well. Figure 9. PCM Output Formats Table 1. MPEG Sampling Rates (KHz) MPEG 1 MPEG 2 MPEG 2.5 48 24 12 44.1 22.05 11.025 32 16 8 |
Similar Part No. - STA015_04 |
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Similar Description - STA015_04 |
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