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MK68564N-04 Datasheet(PDF) 11 Page - STMicroelectronics |
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MK68564N-04 Datasheet(HTML) 11 Page - STMicroelectronics |
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11 / 46 page  in the data stream. Note that the CRC generator re- sult (frame check) for SDLC data is also routed through the zero insertion logic. I/O CAPABILITIES The SIO offers the choice of Polling, Interrupt (vec- tored or non-vectored), and DMA Transfer modes to transfer data, status, and control information to and from the CPU or other bus master. Polling. The Polled mode avoids interrupts. Status Registers 0 and 1 are updated at appropriate times for each function being performed (for example, CRC Error status valid at the end of the message). All the interrupt modes of the SIO must be disabled to operate the device in a polled environ- ment. While in its Polling sequence, the CPU examines the status contained in Status Register 0 for each chan- nel. The state of the status bits in Status Register 0 serves as an acknowledge to the Poll inquiry. Status bits D0 and D2 indicate that a receive or transmit da- ta transfer is needed. The rest of the status bits in Status Register 0 indicate special status conditions. The receiver error condition bits in Status Register 1 do not have to be read until the Rx Character Avai- lable status bit in Status Register 0 is set to a one. Interrupts. The SIO offers an elaborate interrupt scheme to provide fast interrupt response in real- time applications. The interrupt vector points to an interrupt service routine in the memory. To service operations in both channels and to eliminate the ne- cessity of writing a status analysis routine (as requi- red for a polling scheme), the SIO can modify the in- terrupt vector so it points to one of eight interrupt ser- vice routines. This is done under program control by setting the Status Affects Vector bit in the Interrupt Control Register of channel A or channel B, to a one. When this bit is set, the interrupt vector is modified according to the assigned priority of the various in- terrupting conditions. Note : If the Status Affects Vector bit is set in either channel, the vector is modified for both channels. This is the only control bit that operates in this man- ner in the SIO. Transmit interrupts, Receive interrupts, and Exter- nal/Status interrupts are the sources of interrupts. Each interrupt source is enabled under program control with Channel A having a higher priority than Channel B, and with Receiver, Transmitter, and Ex- ternal/Status interrupts prioritized in that order within each channel. When the Transmit interrupt is en- abled, the CPU is interrupted by the transmit buffer becoming empty. This implies that the transmitter must have had a data character written into it so t can become empty. When enabled, the receiver can interrupt the CPU in one of three ways : Interrupt On First Character Only Interrupt On All Receive Characters Interrupt On A Special Receive Condition. Interrupt On First Character Only.This mode is normally used to start a software Polling loop or a DMA transfer routine using the RxRDY pin. In this mode, the SIO generates an interrupt on the first character received after this mode is selected and, thereafter, only generates an interrupt if a Special Receive Condition occurs. The Special Receive Conditions that can cause an interrupt in this mode are : Rx Overrun Error, Framing Error (in Asynchro- nous modes), and End Of Frame (in SDLC mode). This mode is reinitialized by the Enable Interrupt On Next Rx Character command. If a Special Receive Condition interrupt occurs in this interrupt mode, the data with the special condition is held in the receive data FIFO until an Error Reset Command is issued. Interrupt On All Receive Characters. In this mode, an interrupt is generated whenever the receive data FIFO contains a character or a Special Receive Condition occurs. The Special Receive Conditions that can cause an interrupt in this mode are : Rx O- verrun Error, Framing Error (in Asynchronous modes), End of Frame (in SDLC mode), and Parity Error (if selected). Interrupt On A Special Receive Condition. The Special Receive Condition interrupt is not, as such, a separate interrupt mode. Before a Special Re- ceive Condition can cause an interrupt, either the In- terrupt On First Character Only or Interrupt On All Receive Characters mode must be selected. The Special Receive Condition interrupt will modify the receive interrupt vector if Status Affects Vector is en- abled. The Special Receive Condition status is dis- played in the upper four bits of Status Register 1. Two of the conditions causing a special receive in- terrupt are latched when they occur ; they are : Parity Error and Rx Overrun Error. These status bits may only be reset by an Error Reset command. When ei- ther of these conditions occur, a read of Status Re- gister 1 will reflect any errors in the current word in the receive buffer plus any parity or overrun errors since the last Error Reset command was issued. External/Status Interrupts. The main function of the External/Status interrupt is to monitor the signal transitions of the CTS, DCD, and SYNC pins ; how- ever, an External/Status interrupt is also caused by a Transmit Underrun condition or by the detection of a Break (Asynchronous mode) or Abort (SDLC mode) sequence in the received data stream. When any one of the above conditions occur, the exter- MK68564 11/46 |
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