M88 FAMILY

2/7

Figure 2A. PLCC Connections

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

VCC

AD7

AD6

AD5

AD4

PD2

PD1

PD0

PC7

PC6

PC5

PC4

VCC

GND

PC3

PC2

PC1

PC0

8

9

10

11

12

13

14

15

16

17

18

19

20

46

45

44

43

42

41

40

39

38

37

36

35

34

AI02857

Figure 2B. PQFP Connections

39 AD15

38 AD14

37 AD13

36 AD12

35 AD11

34 AD10

33 AD9

32 AD8

30 AD7

29 AD6

28 AD5

27 AD4

PD2

PD1

PD0

PC7

PC6

PC5

PC4

GND

PC3

PC2

PC1

PC0

1

2

3

4

5

6

7

8

9

10

11

12

13

AI02858

Note: 1. All products support: JTAG serial ISP, MCU parallel ISP, ISP Flash memory, ISP CPLD, Security features, Power Management

Unit (PMU), Automatic Power-down (APD)

2. SRAM may be backed up using an external battery.

Part Number

Primary Flash

Memory

Secondary NVM

I/O Ports Voltage Range

Access Time

M8813F1Y

1 Mbit

256 Kbit EEPROM

16 Kbit

27

4.5-5.5 V

90 ns or

150 ns

M8813F2Y

1 Mbit

256 Kbit Flash memory

16 Kbit

27

M8834F2Y

2 Mbit

256 Kbit Flash memory

64 Kbit

27

M8813F1W

1 Mbit

256 Kbit EEPROM

16 Kbit

27

2.7-3.6 V

150 ns

M8813F2W

1 Mbit

256 Kbit Flash memory

16 Kbit

27

M8834F2W

2 Mbit

256 Kbit Flash memory

64 Kbit

27

Programmability (ISP) to Flash memory and

programmable logic. The result is a simple and

flexible

solution

for

embedded

designs.

FLASH+PSD devices combine many of the

peripheral

functions

found

in

MCU

based

applications. FLASH+PSD provides a glueless

interface

to

most

commonly-used

ROMless

MCUs.

Table 2 summarizes all the devices in the M88

Family.

The CPLD in the FLASH+PSD devices features

an optimized Macrocell logic architecture. The

Macrocell was created to address the unique

requirements of embedded system designs. It

allows direct connection between the system

address/data bus, and the internal FLASH+PSD

registers, to simplify communication between the

MCU and other supporting devices.

The FLASH+PSD device includes a JTAG Serial

Programming

interface,

to

allow

In-System

Programming (ISP) of the entire device. This

feature reduces development time, simplifies the

manufacturing flow, and dramatically lowers the

cost of field upgrades. Using ST’s special Fast-

JTAG programming, a design can be rapidly

programmed into the FLASH+PSD.

The innovative FLASH+PSD family solves key

problems faced by designers when managing

discrete Flash memory devices, such as:

– Complex address decoding

– In-System (first-time) Programming (ISP)

– Concurrent

EEPROM

or

Flash

memory

programming (IAP).